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m HARRIS 1

SEMICONDUCTOR

HARRIS SEMICONDUCTOR
DATA ACQUISITION NEW PRODUCTS

This supplementary data book contains specifications for new products
released since the main Data Acquisition data book last printed in 1991.
Included in this supplementary data book is a listing of all products
described in the main data book. For a complete listing of all Harris
Semiconductor products, please refer to the Product Selection Guide
(PSG-201 S; ordering information below.)

For complete, current and detailed technical specifications on any Harris
devices please contact the nearest Harris sales, representative or distrib-
utor office; or direct literature requests to:

Harris Semiconductor Literature Department
P.O. Box 883, MS CBl-25
Melbourne, FL 32901
FAX 407-724-3937

U.S. HEADQUARTERS

Harris Semiconductor
1301 Woody Burke Road
Melbourne, Florida 32902
TEL: (407) 724-3000

SOUTH ASIA

Harris Semiconductor H.K. Ltd
13/F Fourseas Building
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Hong Kong
TEL: (852) 723-6339

EUROPEAN HEADQUARTERS

Harris Semiconductor
Mercure Center
100, Ruede la Fusee
1130 Brussels, Belgium
TEL: (32)2 246 21 11

NORTH ASIA

Harris K.K.

Shinjuku NS Bldg. Box 6153
2-4-1 Nishi-Shinjuku
Shinjuku-ku, Tokyo 163-08 Japan
TEL: 81-3-3345-8911

See our a pr<
specs in K^I Xlu

DATA ACQUISITION NEW PRODUCTS
TECHNICAL ASSISTANCE

For technical assistance on the Harris products listed in this databook, please contact
the Field Applications Engineering staff available at one of the following Harris Sales

Offices:

UNITED STATES

CALIFORNIA Costa Mesa 71 4-433-0600

San Jose 408-985-7322

Woodland Hills 818-985-7322

FLORIDA Melbourne 407-724-3576

GEORGIA Duluth 404-476-0025

ILLINOIS Schaumburg 708-240-3480

MASSACHUSETTS Burlington 617-221-1850

NEW JERSEY Mt. Laurel 609-727-1 909

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TEXAS Dallas 21 4-733-0800

INTERNATIONAL

FRANCE Paris 33-1-346-54046

GERMANY Munich 49-8-963-81 30

HONGKONG Kowloon 852-723-6339

ITALY Milano 39-2-262-22 1 4 1

JAPAN Tokyo 81-3-345-891 1

KOREA Seoul 82-2-551 -0931

UNITED KINGDOM Camberley 44-2-766-86886

Harris Semiconductor products are sold by description only. All specifications in this
product guide are applicable only to packaged products; specifications for die are
available upon request. Harris reserves the right to make changes in circuit design,
specifications and other information at any time without prior notice. Accordingly the
reader is cautioned to verify that information in this publication is current before plac-
ing orders. Reference to products of other manufacturers are solely for convenience
of comparison and do not imply total equivalency of design, performance, or otherwise

m HARRIS

\MJ SEMICONDUCTOR

DATA ACQUISITION. -I

NEW PRODUCTS 1

GENERAL INFORMATION

PAGE

MULTIPLEXERS AND SWITCHES DATA SHEETS

DG401 , Monolithic Dual CMOS Analog Switches 1-9

DG403,
DG405

DG408, Single 8-Channel/Differential 4-Channel CMOS Analog Multiplexers 1-11

DG409

DG411, Monolithic Quad SPST CMOS Analog Switches 1-13

DG412,
DG413

DG441, Monolithic Quad SPST CMOS Analog Switches 1-14

DG442

DG458, Single 8 Channel/Differential 4-Channel Fault Protected Analog Multiplexers 1-15

DG459

A/D CONVERTER DATA SHEETS

HI-574A Fast, Complete 12-Bit A/D Converter with Microprocessor Interface 1-17

HI-674A 12|xs, Complete 12-Bit A/D Converter with Microprocessor Interface 1-28

HI-774 8ns, Complete 12-Bit A/D Converter with Microprocessor Interface 1-39

HI-5700 8-Bit, 20 MSPS Flash A/D Converter 1-51

HI-5700/883 8-Bit, 20MSPS Flash A/D Converter 1-62

HI-5701 6 Bit, 30 MSPS Flash A/D Converter 1-71

HI5800 12-Bit, 3MSPS Sampling A/D Converter 1-82

HI5801 12-Bit, 5MSPS A/D Converter 1-94

HI5812 CMOS 12-Bit Sampling A/D Converter with Internal Track and Hold 1-95

HI-7153/883 8-Channel, 10-Bit, High Speed Sampling A/D Converter 1-108

AN9203 Using the HI5800 Evaluation Board 1-120

BR-007 Harris Semiconductor Sales, Representatives and Distributor Locations 1-132

OTHER DATA ACQUISITION PRODUCTS CONTAINED IN MAIN DATA BOOK DB301 1-3

1-1

Other Data Acquisition Products Contained in
Main Data Acquisition Data Book (DB301.1)

AD590

2-Wire Current Output Temperature Transducer

AD7520

10-Bit Multiplying D/A Converter

AD7521

12-Bit Multiplying D/A Converter

AD7523

8-Bit Multiplying D/A Converter

AD7530

10-Bit Multiplying D/A Converter

AD7531

12-Bit Multiplying D/A Converter

AD7533

10-Bit Multiplying D/A Converter

AD7541

12-Bit Multiplying D/A Converter

AD7545

12-Bit Buffered Multiplying CMOS DAC

ADC0802

8-Bit u.P-Compatible A/D Converter

ADC0803

8-Bit uP-Compatible A/D Converter

ADC0804

8-Bit uP-Compatible A/D Converter

CA3161

BCD to Seven Segment Decoder/Driver

CA3304

CMOS Video-Speed 4-Bit Flash A/D Converter

CA3306

CMOS Video-Speed 6-Bit Flash A/D Converter

CA3310/CA3310A

CMOS 10-Bit A/D Converter with Internal Track and Hold

CA3318C

CMOS Video-Speed 8-Bit Flash A/D Converter

CA3338

CMOS Video-Speed 8-Bit R-2R D/A Converter

DG180

Dual SPST 10 Ohm High-Speed Driver with JFET Switch

DG181

Dual SPST 30 Ohm High-Speed Driver with JFET Switch

DG182

Dual SPST 75 Ohm High-Speed Driver with JFET Switch

DG183

Dual DPST 10 Ohm High-Speed Driver with JFET Switch

DG184

Dual DPST 30 Ohm High-Speed Driver with JFET Switch

DG185

Dual DPST 75 Ohm High-Speed Driver with JFET Switch

DG186

SPDT 10 Ohm High-Speed Driver with JFET Switch

DG187

SPDT 30 Ohm High-Speed Driver with JFET Switch

DG188

SPDT 75 Ohm High-Speed Driver with JFET Switch

DG189

Dual SPDT 10 Ohm High-Speed Driver with JFET Switch

DG190

Dual SPDT 30 Ohm High-Speed Driver with JFET Switch

DG191

Dual SPDT 75 Ohm High-Speed Driver with JFET Switch

DG200

Dual SPST CMOS Analog Switch

DG201

Quad SPST CMOS Analog Switch

DG201A

Quad Monolithic SPST CMOS Analog Switch

DG202

Quad Monolithic SPST CMOS Analog Switch

DG211

Quad Monolithic SPST CMOS Analog Switch

DG212

Quad Monolithic SPST CMOS Analog Switch

1-3

Other Data Acquisition Products Contained in
Main Data Acquisition Data Book (DB301.1) (continued)

DG300A

Dual SPST TTL Compatible CMOS Analog Switch

DG301A

SPDT TTL Compatible CMOS Analog Switch

DG302A

Dual DPST TTL Compatible CMOS Analog Switch

DG303A

Dual SPDT TTL Compatible CMOS Analog Switch

DG308A

Quad Monolithic SPST CMOS Analog Switch

DG309

Quad Monolithic SPST CMOS Analog Switch

DG506A

16-Channel CMOS Analog Multiplexer.

DG507A

Dual 8-Channel CMOS Analog Multiplexer

DG508A

8-Channel CMOS Analog Multiplexer

DG509A

Dual 4-Channel CMOS Analog Multiplexer

DG526

16-Channel CMOS Latchable Multiplexer

DG527

Dual 8-Channel CMOS Latchable Multiplexer

DG528

8-Channel Latchable Multiplexer

DG529

Dual 4-Channel Latchable Multiplexer

HI-200

Dual SPST CMOS Analog Switch

HI-201

Quad SPST CMOS Analog Switch

HI-201HS

High-Speed Quad SPST CMOS Analog Switch.

HI-222

High Frequency Video Switch

HI-300

Dual SPST CMOS Analog Switch

HI-301

SPDT CMOS Analog Switch

HI-302

Dual DPST CMOS Analog Switch

HI-303

Dual SPDT CMOS Analog Switch

HI-304

Dual SPST CMOS Analog Switch

HI-305

SPDT CMOS Analog Switch

HI-306

Dual DPST CMOS Analog Switch

HI-307

Dual SPDT CMOS Analog Switch

HI-381

Dual SPST CMOS Analog Switch

HI-384

Dual DPST CMOS Analog Switch

HI-387

SPDT CMOS Analog Switch

HI-390

Dual SPDT CMOS Analog Switch

HI-506

Single 16-Channel CMOS Analog Multiplexer

HI-506A

Single 16-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-507

Differential 8-Channel CMOS Analog Multiplexer

HI-507A

Differential 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protect

HI-508

Single 8-Channel CMOS Analog Multiplexer

HI-508A

Single 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protection.

1-4

Other Data Acquisition Products Contained in
Main Data Acquisition Data Book (DB301.1) (continued)

HI-509

Differential 4-Channel CMOS Analog Multiplexer

HI-509A

Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-516

Programmable 16-Channel/Differential 8-Channel CMOS High-Speed Analog Multiplexer

HI-518

Programmable 8-Channel/Differential 4-Channel CMOS High-Speed Analog Multiplexer

HI-524

4-Channel Wideband and Video Multiplexer

HI-539

Monolithic, 4-Channel, Low Level, Differential Multiplexer

HI-546

Single 16-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-547

Differential 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-548

Single 8-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-549

Differential 4-Channel CMOS Analog Multiplexer with Active Overvoltage Protection

HI-562A

12-Bit High-Speed Monolithic D/A Converter

HI-565A

High-Speed Monolithic D/A Converter with Reference

HI-574A

Fast, Complete 12-Bit A/D Converter with Microprocessor Interface

HI-674A

12u.s, Complete 12-Bit A/D Converter with Microprocessor Interface

HI-774

8ns, Complete 12-Bit A/D Converter with Microprocessor Interface

HI-1818A

Low Resistance Single 8-Channel CMOS Analog Multiplexer

HI-1828A

Low Resistance Differential 4-Channel CMOS Analog Multiplexer

HI-5040

SPST CMOS Analog Switch

Ht-5041

Dual SPST CMOS Analog Switch

HI-5042

SPDT CMOS Analog Switch

HI-5043

Dual SPDT CMOS Analog Switch

HI-5044

DPST CMOS Analog Switch

HI-5045

Dual DPST CMOS Analog Switch

HI -5046

DPDT CMOS Analog Switch

HI-5046A

DPDT CMOS Analog Switch

HI -5047

4PST CMOS Analog Switch

HI-5047A

4PST CMOS Analog Switch

HI-5048

Dual SPST CMOS Analog Switch

HI-5049

Dual DPST CMOS Analog Switch

HI-5050

SPDT CMOS Analog Switch

HI-5051

Dual SPDT CMOS Analog Switch

HI-5700

8-Bit, 20MSPS Flash A/D Converter

HI-5701

6-Bit, 30MSPS Flash A/D Converter

HI-7151

10-Bit High-Speed A/D Converter with Track and Hold

HI-7152

10-Bit High-Speed A/D Converter with Track and Hold

HI-7153

8-Channel 10-Bit High Speed Sampling A/D Converter

1-5

Other Data Acquisition Products Contained in
Main Data Acquisition Data Book (DB301.1) (continued)

HI-7159A

Microprocessor Compatible 5 1/2-Digit A/D Converter

HI-DAC80V

12-Bit, Low Cost Monolithic D/A Converter

HI-DAC85V

12-Bit, Low Cost Monolithic D/A Converter

ICL232

+5 Volt Powered Dual RS-232 Transmitter/Receiver

ICL71C03/ICL8052

Precision 4 1/2-Digit A/D Converter

ICL71C03/ICL8068

Precision 4 1/2-Digit A/D Converter

ICL7104/ICL8052

14/16-Bit nP-Compatible 2-Chip A/D Converter

ICL7104/ICL8068

14/16-Bit nP-Compatible 2-Chip A/D Converter

ICL7106

3 1/2-Digit LCD Single-Chip A/D Converter

ICL7107

3 1/2-Digit LED Single-Chip A/D Converter

ICL7109

12-Bit uP-Compatible A/D Converter

ICL7115

14-Bit High-Speed CMOS uP-Compatible A/D Converter

ICL7116

3 1/2-Digit with Display Hold Single-Chip A/D Converter

ICL7117

3 1/2-Digit with Display Hold Single-Chip A/D Converter

ICL7121

16-Bit Multiplying Microprocessor-Compatible D/A Converter

ICL7126

3 1/2-Digit Low Power Single-Chip A/D Converter

ICL7129

4 1/2-Digit LCD Single-Chip A/D Converter

ICL7134

14-Bit Multiplying uP-Compatible D/A Converter

ICL7135

4 1/2-Digit BCD Output A/D Converter

ICL7136

3 1/2-Digit LCD Low Power A/D Converter

ICL7137

3 1/2-Digit LED Low Power Single-Chip A/D Converter

ICL7139

3 3/4-Digit Autoranging Multimeter

ICL7149

Low Cost 3 3/4-Digit Autoranging Multimeter

ICL8052

A/D Converter - Low Leakage, Low Noise

ICL8068

A/D Converter - Low Leakage, Low Noise

ICL8069

Low Voltage Reference

iai m~t -4 -?r\

ICM7170

u.P-Compatible Real-Time Clock

ICM7207/A

CMOS Timebase Generator

ICM7208

7-Digit LED Display Counter

ICM7209

Timebase Generator

ICM7211

4-Digit LCD Display Driver

ICM7212

4-Digit LED Display Driver

ICM7213

One Second/One Minute Timebase Generator

ICM7216A/B/D

8-Digit Multi-Function Frequency Counter/Timer

ICM7217

4-Digit LED Display Programmable Up/Down Counter

ICM7218

8-Digit LED Multiplexed Display Driver

ICM7224

4 1/2-Digit LCD/LED Display Counter

Other Data Acquisition Products Contained in
Main Data Acquisition Data Book (DB301.1) (Continued)

ICM7226A/B

8-Digil Multi-Function Frequency Counter/Timer

ICM7228

8-Digit LED Multiplexed Display Driver

ICM7231

Numeric/Alphanumeric Triplexed LCD Display Driver

ICM7232

Numeric/Alphanumeric Triplexed LCD Display Driver

ICM7243

8-Character uP-Compatible LED Display Driver

ICM7249

5 1/2-Digit LCD u-Power Event/Hour Meter

IH401A

Quad Varafet Analog Switch

IH5009

Quad 100 Ohm Virtual Ground Analog Switch

IH5010

Quad 150 Ohm Virtual Ground Analog Switch

IH5011

Quad 100 Ohm Virtual Ground Analog Switch

IH5012

Quad 150 Ohm Virtual Ground Analog Switch

IH5014

Triple 150 Ohm Virtual Ground Analog Switch

IH5016

Triple 150 Ohm Virtual Ground Analog Switch

IH5017

Dual 100 Ohm Virtual Ground Analog Switch

IH5018

Dual 150 Ohm Virtual Ground Analog Switch

IH5019

Dual 100 Ohm Virtual Ground Analog Switch

IH5020

Dual 150 Ohm Virtual Ground Analog Switch

IH5022

Single 150 Ohm Virtual Ground Analog Switch

IH5024

Single 150 Ohm Virtual Ground Analog Switch

IH5043

Dual SPDT 75 Ohm High-Level CMOS Analog Switch

IH5052

Quad SPST CMOS Analog Switch

IH5053

Quad SPST CMOS Analog Switch

IH5140

SPST High-Level CMOS Analog Switch

IH5141

Dual SPST High-Level CMOS Analog Switch

IH5142

SPDT High-Level CMOS Analog Switch

IH5143

Dual SPDT High-Level CMOS Analog Switch

IH5144

DPST High-Level CMOS Analog Switch

IH5145

Dual DPST High-Level CMOS Analog Switch

IH5151

Dual SPDT High-Level CMOS Analog Switch

IH5341

Dual SPST CMOS RF/Video Switch

IH5352

Quad SPST CMOS RFA/ideo Switch

IH6108

8-Channel CMOS Analog Multiplexer

IH6201

Dual CMOS Driver/Voltage Translator

IH6208

4-Channel Differential CMOS Analog Multiplexer

IM6654

4096-Bit CMOS UV EPROM

1-7

SEMICONDUCTOR

PRELIMINARY

July 1992

DG401, DG403
DG405

Monolithic Dual CMOS
Analog Switches

Features

• ON-Resistance < 350.

• Low Power Consumption (P D < 35uW)

• Fast Switching Action

- t ON <150ns

- t OFF <100ns

Low Charge Injection

DG401 Dual SPST; Same Plnout as HI5041

DG403 Dual SPDT; DG190, IH5043, IH5151

DG405 Dual DPST; DG184, HI5045, IH5145

TTL, CMOS Compatible

Single or Split Supply Operation

Benefits
Low Signal Errors and Distortion
Reduced Power Supply
Faster Throughput
Improved Reliability
Reduced Pedestal Error
Simplifies Retrofit
Simple Interfacing
Break-Before-Make

Applications
Audio Switching
Battery Operated Systems
Data Acquisition
Hi-Rel Systems
Sample and Hold Circuits
Communication Systems
Automatic Test Equipment

Description

The DG401, DG403 and DG405 monolithic CMOS analog
switches have TTL & CMOS compatible digital inputs, and a
voltage reference for logic thresholds.
These switches feature low analog ON resistance (< 3511)
and fast switch time (toN < 1 50ns). Low charge injection sim-
plifies sample and hold applications.
The improvements in the DG401/403/405 series are made
possible by using a high voltage silicon-gate process. An
epitaxial layer prevents the latch-up associated with older
CMOS technologies. The 44V maximum voltage range per-
mits controlling 30V peak-to-peak signals. Power supplies
may be single-ended from +5V to +34V, or split from ±5V to
±17V.

The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with ana-
log signals is quite low over a ±15V analog input range. The
three different devices provide the equivalent of two SPST
(DG401), two SPDT (DG403) or two DPST (DG405) relay
switch contacts with CMOS or TTL level activation. The
pinout is similar, permittng a standard layout to be used,
choosing the switch function as needed.

Pinouts Switches Shown for Logic "0" Input

DG403

TOP VIEW

D, [7
NCfT
D,U

s«GE —

D 4 [T-o.

NC [7

ills,

if] a,
u\ V-

13] GND

9]S 2

(NC) NO CONNECTION

CAUTION: These devices are sensitive to electrostatic discharge. Users should tollow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1992 1 „

File Number 3284

DG401, DG403, DG405

Truth Table

LOGIC

DG401

DG403

DG405

SWITCH

SWITCH 1,2

SWITCH 3, 4

SWITCH

OFF

NOTE: Logic "0" <0.8V. Logic T 22.4V.

1-10

SEMICONDUCTOR

PRELIMINARY

July 1992

DG408
DG409

Single 8-Channel/Differential
4-Channel CMOS Analog Multiplexers

Features

ON-Resistance 100Q Maximum (+25°C)
Low Power Consumption (P D < 11 mW)
Fast Switching Action

- ^trans * 250ns

- toN/OFF(EN) < 150n8

Low Charge Injection
Upgrade from DG5067DG509
TTL, CMOS Compatible Logic
Single or Split Supply Operation

Benefits
Low Signal Errors and Distortion
Reduced Power Supply
Faster Throughput
Improved Reliability
Break-Before-Make Switching
Simplifies Retrofit
Simple Interfacing

Applications

Data Acquisition Systems
Audio Switching Systems
Automatic Testers
Hi-Rel Systems
Sample and Hold Circuits
Communication Systems
Analog Selector Switch

Description

The DG408 Single 8-Channel and DB409 Differential 4-
Channel monolithic CMOS analog multiplexers are drop-in
replacements for the popular DG508 and DG509 series
devices. They each include an array of eight analog
switches, a TTL/CMOS compatible digital decode circuit for
channel selection, a voltage reference for logic thresholds
and an ENABLE input for device selection when several mul-
tiplexers are present.

The feature lower signal ON resistance (< 100Q) and faster
switch transition time (Itrans < 250ns) compared to the
DG508A or DG509A. Charge injection has been reduced,
simplifying sample and hold applications. The improvements
in the DG408 series are made possible by using a high-volt-
age silicon-gate process. An epitaxial layer prevents the
latch-up associated with older CMOS technologies.

The 44V maximum voltage range permits controlling 30V
peak-to-peak signals. Power supplies may be single-ended
from +5V to +34V, or split from ±5V to ±17V.

The analog switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with ana-
log signals is quite low over a ±5V analog input range.

Pinouts

DG408

TOP VIEW

ENABLE [7

" V SUPPLY L?
IN1 [7
IN2 [7
IN3 [T
IN4 [7
OUT [7

16] A,

111*2
U\ GND

fj] INS
]TJ IN6
10] IN7
JJlNB

DG409

TOP VIEW

Ao[T
ENABLE [7
-Vsupply [7
IN1A [7
IN2A [7
IN3A |T
IN4A [7
OUTA (7

!UAi

IS] GND

j3 +Vsupp L Y

13] IN1B

j|]lN2B

il]lN3B

10]lN4B

JJOUTB

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

File Number 3280

1-11

DG408, DG409

Functional Block Diagrams

DG408

DG409

IN1

IN2 i

DECODER/
DRIVER

* DIGITAL
INPUT

PROTECTION

-o OUT

Ao A, A 2 EN

IN1A <

i
i

IN4A l

IN1B i

<
i

IN4B '

-o OUTB

DECODER/
DRIVER

SV
REF

LEVEL
SHIFT

* DIGITAL
INPUT

PROTECTION

Ag A, EN

Truth Tables

ON SWITCH

NONE

NOTES:

1. V^h Logic "1" a 2.4V

2. Logic -0- S0.8V

DG409

ON SWITCH

NONE

1-12

SEMICONDUCTOR

PRELIMINARY

July 1992

DG411, DG412
DG413

Monolithic Quad SPST CMOS
Analog Switches

Features

ON- Resistance < 35a max

Low Power Consumption (P D < 3SuW)

Fast Switching Action

- 1 on <175ns

- topp <145ns

Low Charge Injection
Upgrade from DG201 A/DG202
TTL, CMOS Compatible
Single or Split Supply Operation

Benefits
Low Signal Errors and Distortion
Reduced Power Supply
Faster Throughput
Improved Reliability
Reduced Pedestal Error
Simplifies Retrofit
Simple Interfacing

DG413 has Two NC, Two NO Switches

Applications

Audio Switching

Battery Operated Systems

Data Acquisition

Hi-Rel Systems

Sample and Hold Circuits

Communication Systems

Automatic Test Equipment

Description

The DG411 series monolithic CMOS analog switches are drop-in
replacements for the popular DG201A and DG202 series devices. They
include four independent single pole throw (SPST) analog switches, TTL
and CMOS compatible digital inputs and a voltage reference for logic
thresholds.

These switches feature lower analog ON resistance (< 35Q.) and faster
switch time (toN < 175ns) compared to the DG201A or DG202. Charge
injection has been reduced, simplifying sample and hold applications.

The improvements in the DG411 series are made possible by using a
high voltage silicon-gate process. An epitaxial layer prevents the latch-up
associated with older CMOS technologies. The 44V maximum voltage
range permits controlling 30V peak-to-peak signals. Power supplies may
be single-ended from +5V to +34V, or split from ±5V to ±17V.

The four switches are bilateral, equally matched for AC or bidirectional
signals. The ON resistance variation with analog signals is quite low over
a ±15V analog input range. The switches in the DG411 and DG412 are
identical, differing only in the polarity of the selection logic. Two of the
switches in the DG413 (#1 and #4) use the logic of the DG201A/DG411
(i.e. a logic "0" turns the switch ON) and the other two switches use
DG202/DG412 positive logic. This permits independent control of turn-
on and turn-off times for SPDT configurations, permitting "break-before-
make" or "make-before-break" operation with a minimum of external
logic.

Truth Table

DG411

DG412

DG413

LOGIC

SWITCH

SWITCH 1,4

SWITCH 2, 3

OFF

NOTE: Logic "0" <0.8V. Logic "1 * >2.4V.

Pinout

IN, |T
D, [2
S, |T
V-[T
GND jT
S 4 [6
D t \7

IN, [7

TOP VIEW
\J

16] IN 2

ijD 2
U]S 2

i3] v+

12] NC

iTJs 3

iojDa

9]lN 3

(NC) NO CONNECTION

Functional Diagrams Four SPST Switches per Package Switches Shown tor Logic "1" Input
DG411 DG412 DG413

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper US. Handling Procedures. R | e N ur rit>er 3281

SEMICONDUCTOR

PRELIMINARY

July 1992

DG441
DG442

Monolithic Quad SPST CMOS
Analog Switches

Features

ON-Resistance 85ft max

Low Power Consumption (P D < l.6mW)

Fast Switching Action

- t 0N < 250ns

- t OFF < 120ns (DG441)
Low Charge Injection
Upgrade from DG201 A/DG202
TTL, CMOS Compatible
Single or Split Supply Operation

Benefits
Low Signal Errors and Distortion
Reduced Power Supply
Faster Throughput
Improved Reliability
Reduced Pedestal Error
Simplifies Retrofit
Simple Interfacing

Applications

Audio Switching

Battery Operated Systems

Data Acquisition

Hi-Rel Systems

Sample and Hold Circuits

Communication Systems

Automatic Test Equipment

Description

The DG441 and DG442 monolithic CMOS analog switches
are drop-in replacements for the popular DG201A and
DG202 series devices. They include four independent single
pole single throw (SPST) analog switches, TTL and CMOS
compatible digital inputs and a voltage reference for logic
thresholds.

These switches feature lower analog ON resistance (<85£i)
and faster switch time (to N < 250ns) compared to the
DG201A and DG202. Charge injection has been reduced,
simplifying sample and hold applications.

The improvements in the DG441 series are made possible
by using a high voltage silicon-gate process. An epitaxial
layer prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits con-
trolling 30V peak-to-peak signals. Power supplies may be
single-ended from +5V to +34V, or split from ±5V to ±7V.

The four switches are bilateral, equally matched for AC or
bidirectional signals. The ON resistance variation with ana-
log signals is quite low over a ±5V analog input range. The
switches in the DG441 and DG442 are identical, differing
only in the polarity of the selection logic.

Pinout

TOP VIEW

IN, [7

16] IN 2

°l[Z

1S]D 2

S, |T

14] Sj

VI [4

13] v+

GND [T

12] NC

S 4 [6

ID S3

D«E

10] Da

IN 4 [I

3 "N,

(NC) NO CONNECTION

Functional Diagrams

00441

DG442

IN 2 c

IN 3 <

Truth Table

LOGIC

VIN

DG441

DG442

<0.8V

OFF

>2.4V

OFF

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.e. Handl

1-14

File Number

SEMICONDUCTOR

PRELIMINARY

July 1992

DG458
DG459

Single 8 Channel/Differential 4-ChanneI
Fault Protected Analog Multiplexers

Features

Fault and Overvoltage Protection
ON-Resistance < 1.8KO (+25°C)
Low Power Consumption (P D < 6mW)
Fast Switching Action
- ^trans < 500ns

■ l ON/OFF(EN) < 250nS

Fail Safe with Power Loss (No Latch-Up)
Upgrade from DG508/DG509
TTL, CMOS Compatible Logic

Benefits

Low Signal Errors and Distortion
Reduced Power Supply
Faster Throughput
Improved Reliability
Break-Before-Make Switching
Simplifies Retrofit
Simple Interfacing

Applications
Data Acquisition Systems
Audio Switching Systems
Automatic Testers
Hi-Rel Systems
Sample and Hold Circuits
Communication Systems
Analog Selector Switch

Description

The DG458 Single 8-Channel and DB459 Differential 4-
Channel monolithic CMOS analog multiplexers are drop-in
replacements for the popular DG508 and DG509 series
devices. They each include an array of eight analog
switches, a series N-channel/P-channel/N-channel fault pro-
tection circuit, a TTL/CMOS compatible digital decode circuit
for channel selection, a voltage reference for logic thresholds
and an ENABLE input for device selection when several mul-
tiplexers are present.

The feature lower signal ON resistance (< 100O) and faster
switch transition time (t TRANS < 250ns) compared to the
DG508A or DG509A. Charge injection has been reduced,
simplifying sample and hold applications. The improvements
in the DG458 series are made possible by using a high-volt-
age silicon-gate process. An epitaxial layer prevents the
latch-up associated with older CMOS technologies.

The 44V maximum voltage range permits controlling 20V
peak-to-peak signals, while withstanding continuous over-
voltages up to ±35V, providing an open fault circuit.

The analog switches are bilateral, break-before-make,
equally matched for AC or bidirectional signals. The ON
resistance variation with analog signals is quite low over a
±5V analog input range.

Pinouts

DG458 DG459

TOP VIEW TOP VIEW

AoLT

16] A,

Ao[T

16] A,

ENABLE [2

if]A 2

ENABLE (T

IS] GND

-Vsupply [3

14] GND

-Vsupply [£

3 +V SUPPLY

IN1 [7

13] +VSUPPLY

IN1A (T

13] IN1B

IN2 [7

12] INS

IN2A (T

12] IN2B

INS [T

11] INS

IN3A [7

n] IN3B

IN4 [7

ij>]iN7

IN4A [7

I0]|N4B

OUTg

9]lN8

OUTA g

JJOUTB

CAUTION: These devices are sensitive to eleclrostatic discharge. Users should follow proper I.O. Handling Procedures.
Copyright ©Harris Corporation 1992 1 1 _

File Number 3280

DG458, DG459

Functional Block Diagrams

DG458

DECODER/
DRIVER

SV
REF

LEVEL
SHIFT

* DIGITAL
INPUT

PROTECTION

-o OUT

Ao A, A 2 EN

IN1A l

* DIGITAL
INPUT

PROTECTION

Ao A,

> OUT A

-o OUT B

Truth Tables

DG458

ON SWITCH

NONE

NOTES:

1. Vah Logic T> 2.4V

2. v*,. Logic -CT <0.8V

DG459

ON SWITCH

NONE

1A, 1B

2A, 2B

3A.3B

4A.4B

1-16

ffj HARRIS

I^Lr semiconductor

HI-574A

June 1992

Features

• Complete 12-Blt A/D Converter with Reference and
Clock

• Full 8-, 12- or 16-Bit Microprocessor Bus Interface

• 150ns Bus Access Time

• No Missing Codes Over Temperature

• Minimal Setup Time for Control Signals

• 25ns Maximum Conversion Time

• Low Noise, via Current-Mode Signal Transmission
Between Chips

• Byte Enable/Short Cycle (A Q Input)

- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
the Start Convert Input (To Set the Conversion
Length)

• Improved Second Source for AD574A

• ±12V to ±1SV Operation

Applications

• Military and Industrial Data Acquisition Systems

• Electronic Test and Scientific Instrumentation

• Process Control Systems

Fast, Complete 1 2-Bit A/D Converter
with Microprocessor Interface

Description

The HI-574A is a complete 12-bit Analog-to-Digital Converter,
including a +10V reference, clock, three-state outputs and a
digital interface for microprocessor control. Successive
approximation conversion is performed by two monolithic dice
housed in a 28 pin package. The bipolar analog die feature
the Harris Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up.

Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital IC's. Also, the clock oscillator is current
controlled for excellent stability over temperature. The oscil-
lator is trimmed for a nominal conversion time of 20 ±1us.

The HI-574A offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The buried zener reference circuit is trimmed for
minimum temperature coefficient.

Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385m W at ±12V. For MIL-STD-883 compliant
parts, request the HI-574A/883 data sheet.

Pinout

PLASTIC AND SIDEBRAZE DIP

TOP VIEW

+5V SUPPLY, Vlqqk; |T
DATA MODE SEL, 12* [T

CHIPSEL.CS [T

BYTE ADDR/SHORT rT
CYCLE, Aq LI

READ/CONVERT, R/C fT
CHIP ENABLE, CE [T
+12V/+15V SUPPLY, V cc [T
+10V REF, REF OUT [T

ANALOG rS -
*ON, AC LI

EWPUT Qo

-12W-15V SUPPLY, V E [7f

BIPOLAR OFFSET T7;

BIP OFF Ul

10V INPUT [13
20V INPUT

28] STATUS, STS
27] DB11,
26] DB10
25] DBS
24] DBS
23] DB7
22] DB6
2l]DB5
20]DB4
l5]DB3
l5]oB2

it]dbi

16]DB0,L
15] DIG COMMON, DC

DIGITAL
)> DATA
OUTPUTS

Ordering Information

PART
NUMBER

INL

TEMP.
RANGE

PACKAGE

HI3-574AJN-5

+1.0LSB

0°C to +75°C

28 Pin Plastic DIP

HI3-574AKN-5

±0.5LSB

0°C to +75°C

28 Pin Plastic DIP

HI1-574AJD-5

+1 .0LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-574AKD-S

±0.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-574ALD-5

±0.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-574ASD-2

±1.0LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-574ATD-2

±0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-S74AUD-2

±0.5LSB

-SS°Cto+125°C

28 Pin Ceramic DIP

HI1-574ASD/8B3

±1.0LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-574ATD/883

+0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-574AUD/883

±0.5LSB

-55°C1o+125°C

28 Pin Ceramic DIP

HI4-574ASE/883

±1.0LSB

-55°CIO+125°C

44 Pin Ceramic LCC

HI4-574ATE/883

±0.5LSB

-55°C to +125°C

44 Pin Ceramic LCC

HI4-574AUB883

±0.5LSB

-55 Cto+125 C

44 Pin Ceramic LCC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I C. Handling Procedures.
Copyright © Harris Corporation 1992

File Number 3096.1

HI-574A

Functional Block Diagram

BIT OUTPUTS
A

MSB LSB
009990090009

12/8 o-
CS o-
Ao«-

R/C o-
CE o-

Vhef"n o-

Vref OUT 0-

CONTROL
LOGIC

NIBBLE* A

NIBBLE* B

NIBBLE* C

THREE-STATE BUFFERS AND CONTROL

OSCILLATOR

POWER-UP RESET

cue

] "^12MTSp

SAR

DIGITAL CHIP

ANALOG CHIP

12 BITS

STROBE

+10V
REF.

DAC

^ 5K> iok :

ANALOG

5k:

11 y.

BIP. 20V 10V
OFF INPUT INPUT

-o Vlogic

DIGITAL
' COMMON

-o STS

-o v CC

-o V EE

* "Nibble" is a 4 bit digital word

Specifications HI-574A

Absolute Maximum Ratings

Supply Voltage

V cc to Digital Common OV to +16.5V

V EE to Digital Common OV to -16.5V

v logic ,0 Digital Common OV to +7V

Analog Common to Digital Common ±1V

Control Inputs

(CE, CS, Aq, 12/8, R/C) to Digital Common . . . .-0.5V to V LOG ic+0.5V
Analog Inputs

(REFIN, BIPOFF, 10VIN) to Analog Common ±16.5V

20VIN to Analog Common ±24V

REFOUT Indefinite short to Common, momentary short to Vcc

Operating Temperature Range

HI3-574AxN-5, HI1-574AxD-5 0°C to +75°C

HI1-574AXD-2 -55°C to +125°C

Junction Temperature

HI3-574AXN-5 +150°C

HI1-574AXD-2, HI1-574AXD-5 +175°C

Storage Temperature Range

HI3-574AxN-5 -40°C < T A < +85°C

HI1-574AxD-2, HI1-574AxD-5 -65°C < T A < +1 50°C

Lead Temperature (Soldering, 10s) 300°C

CAUTION: Slresses above those listed in 'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Information

Thermal Resistance 6j. 6^

HI3-574AxN-5 75°C/W

HI1-574AXD-2, HI1-574AXD-5 48°C/W 15°CAV

Power Dissipation at 75°C (Note 1)

HI3-574AXN-5 1000mW

HI1-574AXD-2, HI1-574AxD-5 2083mW

Power Dissipation Derating Factor Above +75°C

HI3-574AXN-5 13.3mW/°C

HI1-574AXD-2, HI1-574AxD-5 20.8mW/°C

Transistor Count 1117

NOTE:

1 . Dissipation rating assumes device is mounted with all leads sol-
dered to printed circuit board.

rating and operation

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOGIC = +5V, v EE = -15V or -12V,

Unless Otherwise Specified

TEMPERATURE RANGE

-5 (0°C to +75°C)

PARAMETERS

HI-574AJ

HI-574AK

HI-574AL

UNITS

Resolution (max)

Bits

Linearity Error
+25°C (Max)
0°C to +75°C (Max)

±1
±1

±1/2
±1/2

LSB
LSB

Differential Linearity Error

+25°C (Max resolution for which no missing codes is guaranteed)

+25°C

±1
12
11

±1
12
12

±1/2
12
12

LSB
Bits
Bits

Unipolar Offset (max)
Adjustable to Zero

±2

±1.5

±1

LSB

Bipolar Offset (max)

V| N = OV (Adjustable to Zero)
V IN = -10V

±4
±0.15

±4
±0.1

±3
±0.1

LSB
% of F.S.

Full Scale Calibration Error

+25°C (Max), with fixed 50£2 resistor from REF OUT to REF IN

(Adjustable to Zero)
t min 10 t max ( No adjustment at +25°C)
t min 10 t max (With adjustment to zero +25°C)

±0.25

±0.475
±0.22

±0.25

±0.375
0.12

±0.15

±0.20
±0.05

% of F.S.

% Of F.S.
% of F.S.

Temperature Coefficients

Guaranteed max change, T M , N to T MAX (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2(10)
±2(10)
±9 (45)

±1(5)
±1 (5)
±2(10)

LSB (pprrVC)
LSB (ppm/°C)
LSB (ppm/°C)

Power Supply Rejection

Max change in Full Scale Calibration

+13.5V < V cc < +16.5V or +1 1 .4V < V cc < +12.6V

+4.5V < V LOG ic < +5.5V

-16.5V < V EE < -13.5V or -12.6V < V EE < -1 1.4V

±2
±1/2
±2

±1
±1/2
±1

LSB
LSB
LSB

1-19

Specifications HI-574A

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG , c = +5V, v EE = -15V or -12V,

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE
-5 (0°C to +75°C)

PARAMETERS

HI-574AJ |

HI-574AK |

HI-574AL

UNITS

Analog Inputs
Input Ranges
Bipolar

-5 to +5

- 1 U lO + 1 u

V
V

Unipolar

0to+10
to +20

V
V

Input Impedance
10V Span
20V Span

5K, ±25%
10K, +25%

Power Supplies

Operating Voltage Range

V lOGIC

Vcc

Vee

+4.5 to +5.5
+11.410+16.5
-11.4 to -16.5

V
V
V

Operating Current

'logic

Ice +15V Supply
l EE -15V Supply

7Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max

mA
mA
mA

Power Dissipation
±15V, +15V
±12V, +5V

515 Typ, 720 Max
385 Typ

mW
mW

Internal Reference Voltage
T MIN 1° T MAX

Output current (Note 1 ), available for external loads (External load
should not change during conversion).

+10.00 ±0.05 Max
2.0 Max

Volts
mA

NOTE:

1. When supplying an external load (not including the ADC) and operating on +12V supplies, a buffer amplifier must be
Reference Output.

provided for the

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG | C = +5V, v

Unless Otherwise Specified

EE = -15V or -12V,

TEMPERATURE RANGE
-2(+55°Cto+125°C)

PARAMETERS

HI-574AS

HI-574AT

HI-574AU

UNITS

Resolution (max)

Bits

Linearity Error
+25°C (Max)
0°C to +75°C (Max)

i+ i+

±1/2
±1

LSB
LSB

Differential Linearity Error

+25°C (Max resolution for which no missing codes is guaranteed)
+25°C

T MIN 1° T MAX

±1
12
11

±1
12
12

±1/2
12
12

LSB
Bits
Bits

Unipolar Offset (max)
Adjustable to Zero

±2

±1.5

±1

LSB

Bipolar Offset (max)

V, N = 0V (Adjustable to Zero)
V, N = -10V

±4
±0.15

±4

±0.1

±3
±0.1

LSB
% of F.S.

Full Scale Calibration Error

+25°C (Max), with fixed 50Q resistor from REF OUT to REF IN

(Adjustable to Zero)
t min t0 t max ( No adjustment at +25°C)
t min 'o T MAX (With adjustment to zero +25°C)

±0.25

±0.75
+0.50

±0.25

±0.50
0.25

±0.15

±0.275
±0.125

% of F.S.

% of F.S.
% of F.S.

1-20

Specifications HI-574A

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG i C = +5V, v EE = -15V or -12V,

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE

-2(+55°CtO+125 <, C)

PARAMETERS

HI-574AS

HI-574AT

HI-574AU

UNITS

Temperature Coefficients

Guaranteed max change, T M!N to T MAX (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2 (5)
±2(5)
±20 (50)

±1 (2.5)
±2(5)
±10 (25)

±1 (2.5)
±1 (2.5)
±5 (12.5)

LSB (ppnV°C)
LSB (ppnV°C)
LSB (ppnVC)

Power Supply Rejection

MaX Llldliyo 111 run OOdltJ OdIIUIdilON

+13.5V < V cc < +16.5V or +1 1.4V < V cc < +12.6V
44.5V < V L0GIC < +5.5V

-16.5V < V EE < -13.5V or -12.6V < V EE < -11.4V

±2
±1/2
±2

±1
±1/2
±1

±1

±1/2
+1

LSB
LSB
LSB

Analog Inputs
Input Ranges
Bipolar

-5 to +5
-10 to +10

V
V

Unipolar

to +10
to +20

V
V

llipui IliipeudllUfc;

10V Span
20V Span

5kn, +25%
10kn, +25%

Power Supplies

Onpratinn VnltanA Pannp
vjpciidLiny vuiidyu ndiiye

V LOGIC

Vcc
Vee

+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5

V
V
V

Operating Current
'logic

l cc +15V Supply
l EE -15V Supply

7 Typ, 1 5 Max
11 Typ, 15 Max
21 Typ, 28 Max

mA
mA
mA

Power Dissipation
±15V, +15V
±12V, +5V

515 Typ, 720 Max
385 Typ

mW
mW

Internal Reference Voltage

T MIN ,0 T MAX

Output current available for external loads (External load should not
change during conversion).

+10.00 ±0.05 Max
2.0 Max

Volts
mA

Digital Characteristics (Note 1) All Models, Over Full Temperature Range

PARAMETERS

MIN

TYP

MAX

Logic Inputs (CE, CS, R/C, AO, 12/8) (Note 2)

Logic "1"

+2.4V

+5.5V

Logic "0"

-0.5V

+0.8V

Current

-5uA

±0.1 uA

+5uA

Capacitance

5pF

Logic Outputs (DB1 1 -DB0, STS)

Logic "0"(I SINK - 1.6mA)

+0.4V

Logic T (Isource " 500uA)

+2.4V

Leakage (High Z State, DB1 1-DB0 Only)

-5uA

+0.1 uA

+5uA

Capacitance

5pF

NOTES:

1. See "HI-574A Timing Specifications" for a detailed listing of digital timing parameters.

2. Although this guaranteed threshold is higher than standard TTL (+2.0V), bus loading is much less, i.e., typical input current is only 0.25%
of a TTL load.

1-21

Specifications HI-574A

Timing Specifications +25°C, Unless Otherwise Specified

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

CONVERT MODE

tosc

STS Delay from CE

200

•hec

CE Pulse Width

•ssc

CS to CE Setup

'hsc

CS Low During CE High

'SRC

R/C to CE Setup

•hrc

R/C Low During CE High

•sac

Aq to CE Setup

<HAC

Aq Valid During CE High

Conversion Time

1 2 Bit Cycle Ty in to T^^x

8 Bit Cycle T^^ to T^ax

READ MODE

'do

Access Time from CE

150

*HD

Data Valid After CE Low

tHL

Output Float Delay

100

150

•sSR

CS to CE Setup

•SHR

R/C to CE Setup

l SAR

Aq to CE Setup

tHSR

CS Valid After CE Low

'hrr

R/C High After CE Low

•har

Aq Valid After CE Low

•hs

STS Delay After Data Valid

300

1200

NOTE:

1. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kn load.

Definitions of Specifications

Linearity Error

Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale". The point
used as "zero" occurs V 2 LSB (1 .22mV for 1 0V span) before the
first code transition (all zeros to only the LSB "on"). "Full scale"
is defined as a level 1 1 / 2 LSB beyond the last code transition (to
all ones). The deviation of a code from the true straight line is
measured from the middle of each particular code.

The HI-574AK, AL, AT, and AU grades are guaranteed for
maximum nonlinearity of ± 1 / 2 LSB. For these grades, this
means that an analog value which falls exactly in the center
of a given code width will result in the correct digital output
code. Values nearer the upper or lower transition of the code
width may produce the next upper or lower digital output
code. The HI-574AJ and AS grades are guaranteed to
±1LSB max error. For these grades, an analog value which
falls within a given code width will result in either the correct
code for that region or either adjacent one.

Note that the linearity error is not user-adjustable.

Differential Linearity Error (No Missing Codes)

A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing

sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-574AK, AL, AT, and
AU grades, which guarantee no missing codes to 12-bit resolu-
tion, all 4096 codes must be present over the entire operating
temperature ranges. The HI-574AJ and AS grades guarantee
no missing codes to 11 -bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice very few of the 12-bit codes are missing.

Unipolar Offset

The first transition should occur at a level V 2 LSB above ana-
log common. Unipolar offset is defined as the deviation of
the actual transition from that point. This offset can be
adjusted as discussed on the following pages. The unipolar
offset temperature coefficient specifies the maximum
change of the transition point over temperature, with or with-
out external adjustment.

Bipolar Offset

Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an
analog value V 2 LSB below analog common. The bipolar off-
set error and temperature coefficient specify the initial devia-
tion and maximum change in the error over temperature.

1-22

HI-574A

Full Scale Calibration Error

The last transition (from 1111 1111 1110 to 1111 1111
1111) should occur for an analog value 1 1 / 2 LSB below the
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 1 and 2. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.

-1SV

100Q

r-^VW

v4 0TO+10V
ANALOG °

INPUTS ,

TO +20 V

212/8

STS28

3CS

HIGH BITS

24-27

* *0 MIDDLE BITS

20-23

5R/C

LOW BITS

6 CE

16-18

10 REF IN

8 REF OUT

12 BIP OFF

+5V1

13 10V, N

+15V7

14 20V W "

-15V 11

8 ANA COM

DIG COM 1 5

"Whan driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 1. UNIPOLAR CONNECTIONS

Temperature Coefficients

The temperature coefficients for full-scale calibration, unipo-
lar offset, and bipolar offset specify the maximum change
from the initial (+25°C) value to the value at T M!N or T MAX .

Power Supply Rejection

The standard specifications for the HI-574A assume use of
+5.00 and ±15.00 or ±12.00 volt supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.

Code Width

A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values
for which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full scale range or 2.44mV out of 10V for a 12-bit ADC.

GAIN

ioon

±sv

ANALOG °"
INPUTS _

OFFSET

±10V

2 12/8

3 S3

STS28
HIGH BITS
24-27

4Aq |

5 Rye
ecE

MIDDLE BITS

20-23

LOW BITS
18-19

10 REF IN

8 REF OUT

12 BIP OFF

+5V 1

13 10 V, N

+15V7

14 20V IN *

-15V 11

9 ANA COM

DIG COM 15

■When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. BIPOLAR CONNECTIONS

Quantization Uncertainty

Analog-to-digital converters exhibit an inherent quantization
uncertainty of ±V 2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.

Left-justified Data

The data format used in the HI-574A is left-justified. This
means that the data represents the analog input as a frac-
tion of full-scale, ranging from to . This implies a
binary point to the left of the MSB.

Applying the HI-574A

For each application of this converter, the ground connec-
tions, power supply bypassing, analog signal source, digital
timing and signal routing on the circuit board must be opti-
mized to assure maximum performance. These areas are
reviewed in the following sections, along with basic operating
modes and calibration requirements.

PHYSICAL MOUNTING AND LAYOUT CONSIDERATIONS

Layout

Unwanted, parasitic circuit components, (L, R, and C) can
make 12 bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.

The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vectorboard, will have an unpredictable effect on
accuracy.

1-23

HI-574A

In general, sensitive analog signals should be routed
between ground traces and kept well away from digital lines.
If analog and digital lines must cross, they should do so at
right angles.

Power Supplies

Supply voltages to the HI-574A (+15V, -15V and +5V) must
be "quiet" and well regulated. Voltage spikes on these lines
can affect the converter's accuracy, causing several LSB's to
flicker when a constant input is applied. Digital noise and
spikes from a switching power supply are especially trouble-
some. If switching supplies must be used, outputs should be
carefully filtered to assure "quiet" DC voltage at the con-
verter terminals.

Further, a bypass capacitor pair on each supply voltage ter-
minal is necessary to counter the effect of variations in sup-
ply current. Connect one pair from pin 1 to 15 (V L ogic
supply), one from pin 11 to 9 (V cc to Analog Common) and
one from pin 11 to 9 (V E g to Analog Common). For each
capacitor pair, a 10uF tantalum type in parallel with a 0.1(iF
ceramic type is recommended.

Ground Connections

The typical HI-574A ground currents are 5.5mADC into pin 9
(Analog Common) and 7m ADC out of pin 15 (Digital Com-
mon. These pins should be tied together at the package to
guarantee specified performance for the converter. In addi-
tion, a wide PC trace should run directly from pin 9 to (usu-
ally) 15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance
from the system's "single point" ground, make only these
connections to pins 9 and 15: Tie them together at the pack-
age, and back to the system ground with a single path. This
path should have low resistance since it will carry about
1.5mA of DC current. (Code dependent currents flow in the
v cc. v ee and v logic terminals, but not through the
HI-574A's Analog Common or Digital Common).

ANALOG SIGNAL SOURCE

The device chosen to drive the HI-574A analog input will see a
nominal load of 5K£1 (10V range) or 10kO (20V range). How-
ever, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in cur-
rent at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 1 .6us intervals. This requires low output
impedance and fast settling by the signal source.

The output impedance of an op amp, for example, has an
open loop value which, in a closed loop, is divided by the
loop gain available at a frequency of interest. The amplifier
should have acceptable loop gain at 600KHz for use with the
HI-574A. To check whether the output properties of a signal
source are suitable, monitor the 574A's input (pin 13 or 14)
with an oscilloscope while a conversion is in progress. Each
of the twelve disturbances should subside in one microsec-
ond or less. (The comparator decision is made about 1.5us
after each code change from the SAR).

If the application calls for a Sample/Hold to precede the con-
verter, it should be noted that not all Sample/Holds are com-

patible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Harris HA-5320 Sample/Hold, which was designed for use
with the HI-574A.

RANGE CONNECTIONS AND CALIBRATION
PROCEDURES

The HI-574A is a "complete" A/D converter, meaning it is fully
operational with addition of the power supply voltages, a Start
Convert signal, and a few external components as shown in
Figures 1 and 2. Nothing more is required for most applications.

Whether controlled by a processor or operating in the stand-
alone mode, the HI-574A offers four standard input ranges:
0V to +10V, 0V to +20V ±5V and ±10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been dis-
cussed in an earlier section.

Unipolar Connections and Calibration

Refer to Figure 1. The resistors shown* are for calibration of
offset and gain. If this is not required, replace R2 with a 500,
1% metal film resistor and remove the network on pin 12.
Connect pin 12 to pin 9. Then, connect the analog signal to
pin 1 3 for the OV to 1 0V range, or to pin 1 4 for the OV to 20V
range. Inputs to +20V (5V over the power supply) are no
problem - the converter operates normally.

Calibration consists of adjusting the converter's most negative
output to its ideal value (offset adjustment), then, adjusting the
most positive output to its ideal value (gain adjustment). To
understand the procedure, note that in principle, one is setting
the output with respect to the midpoint of an increment of ana-
log input, as denoted by two adjacent code changes. Nominal
value of an increment is one LSB. However, this approach is
impractical because nothing "happens" at a midpoint to indi-
cate that an adjustment is complete. Therefore, calibration is
performed in terms of the observable code changes instead of
the midpoint between code changes.

For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all O's. To do
this, apply an input of +V 2 LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
Rl until the first code transition flickers between 0000 0000
0000 and 0000 0000 0001 .

Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 1 V 2 LSB's below the nominal full scale (+9.9963V for
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.

Bipolar Connections and Calibration

Refer to Figure 2. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiometers
R1 and R2*. If this isn't required, either or both pots may be
replaced by a 50Q, 1% metal film resistor.

HI-574A

Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is sim-
ilar to that for the unipolar ranges as discussed above. First
apply a DC input voltage V 2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between
output codes 0000 0000 0000 and 0000 0000 0001 . Next,
apply a DC input voltage i 1 / 2 LSB's below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110and 1111 1111 1111.

"The 100Q potentiometer R2 provides Gain Adjust for the 10V and
20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 with a 50ft 1% metal film resistor. Then, to
provide Gain Adjust for the 10.24V range, add a 200(1 potentiometer
in series with pin 13. For the 20.48V range, add a 500n potentiome-
ter in series with pin 14.

CONTROLLING THE HI-S74A

The HI-574A includes logic for direct interface to most micro-
processor systems. The processor may take full control of each
conversion, or the converter may operate in the "stand-alone"
mode, controlled only by the R/C input. Full control consists of
selecting an 8 or 12 bit conversion cycle, initiating the conver-
sion, and reading the output data when ready-choosing either
12 bits at once or 8 followed by 4 in a left-justified format. The
five control inputs are all TTL/CMOS-compatible: (12/8, CS, Aq,
R/C and CE). Table 1 illustrates the use of these inputs in con-
trolling the converter's operations. Also, a simplified schematic
of the internal control logic is shown in Figure 3.

"Stand-Alone Operation"

The simptest_ control interface calls for a singe control line con-
nected to R/C. Also, CE and 12/8 are wired high, CS and Aq are
wired low, and the output data appears in words of 12 bits each.

The R/C signal may have any duty cycle within (and includ-
ing) the extremes shown in Figures 4 and 5. In general, data
may be read when R/C is high unless STS is also high, indi-
cating a conversion is in progress. Timing parameters partic-
ular to this mode of operation are listed below under "Stand-
Alone Mode Timing".

STAND-ALONE MODE TIMING

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

•hrl

Low R/C Pulse Width

tos

STS Delay from R/C

200

•hop

Data Valid after R/C Low

•hs

STS Delay after Data Valid

300

1200

tflRH

High R/C Pulse Width

150

tDDR

Data Access Time

150

Time is measured from 50% level of digital transitions. Tested with a
50pF and 3k£l load.

Conversion Length

A Convert Start transition (see Table 1 ) latches the state of
Ao, which determines whether the conversion continues for
12 bits (Aq low) or stops with 8 bits (Aq high). If all 12 bits
are read following an 8 bit conversion, the three LSB's will

EOC13

FIGURE 3. HI-574A CONTROL LOGIC

1-25

HI-574A

tHRL

STS

DB11-DB0

FIGURE 4. LOW PULSE FOR R/C OUTPUTS ENABLED AFTER CONVERSION

R/C

STS

■dor

<hdr

DB11-DB0 HIGH-Z

DATA V

FIGURE 5. HIGH PULSE FOR R/C OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z

read ZERO and DB3 will read ONE. Aq is latched because it
is also involved in enabling the output buffers (see "Reading
the Output Data"). No other control inputs are latched.

TABLE 1. TRUTH TABLE FOR HI-574A CONTROL INPUTS

R/C

12/8

OPERATION

None

Initiate 12 bit conversion

Initiate 8 bit conversion

Initiate 12 bit conversion

Initiate 8 bit conversion

Initiate 12 bit conversion

Initiate 8 bit conversion

Enable 12 bit Output

Enable 8 MSB's Only

Enable 4 LSB's Plus 4 Trailing
Zeroes

Conversion Start

A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so

one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. To assure that a
particular input controls the start of conversion, the other two
should be set up at least 50ns earlier, however. See the
HI-574A Timing Specifications, Convert mode.

This variety of HI-574A control modes allows a simple inter-
face in most system applications. The Convert Start timing
relationships are illustrated in Figure 6.

The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high. (However, if Aq changes state after a conver-
sion begins, an additional Start Convert signal will latch the
new state of Aq, possibly causing a wrong cycle length (8 vs.
12 bits) for that conversion).

Reading the Output Data

The output data buffers remain^ in a high impedance state
unt il four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and Aq. Timing constraints are illus-
trated in Figure 7.

1-26

HI-574A

The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12 or 16 bit data bus. The Aq input is ignored.

With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Aq. This allows an 8 bit data bus to
be connected as shown in Figure 8. Aq is usually tied to the
least significant bit of the address bus, for storing the
HI-574A output in two consecutive memory locations. (With
Aq low, the 8 MSB's only are enabled. With Aq high, 4MSB's
are disabled, bits 4 through 7 are forced to zero, and the 4
LSB's are enabled). This two byte format is considered "left
justified data", for which a decimal (or binary!) point is
assumed to the left of byte 1 :

BYTE 1

BYTE 2

MSB

LSB

Further, Aq may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 8 will never be enabled at the
same time.

A read operation usually begins after the conversion is com-
plete and STS is low. For earliest access to the data how-
ever, the read should begin no later than (t DD + t H s) before
STS goes low. See Figure 7.

cs
R/e

STS
DB11-DB0

•ssc-

«SRC-

*HRC •

•sac

'hac ■

*DSC

<HEC

-'hsc

HIGH IMPEDANCE

CE-

CS-

"3.

R/C
Ao-

STS-

DB11-DB0 -

«SSH 'HSR— ►

-<3RR

tHS-

HIGH IMPEDANCE

' DATA
f~VAUD~

•hd

tHL

FIGURE 7. READ CYCLE TIMING

FIGURE 8. INTERFACE TO AN 8 BIT DATA BUS

FIGURE 6. CONVERT START TIMING

1-27

SEMICONDUCTOR

HI-674A

July 1992

12ns, Complete 12-Bit A/D Converter
with Microprocessor Interface

Features

• Complete 12-Bit A/D Converter with Reference and
Clock

• Full 8-, 12- or 16-Bit Microprocessor Bus Interface

• 150ns Bus Access Time

• No Missing Codes Over Temperature

• Minimal Setup Time for Control Signals

• 15us Maximum Conversion Time

• Low Noise, via Current-Mode Signal Transmission
Between Chips

• Byte Enable/Short Cycle (A Input)

- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
the Start Convert Input (To Set the Conversion Length)

• Faster Version of the HI-574A

• Same Pinout as the HI-574A

• ±12V to ±15V Operation

Applications

• Military and Industrial Data Acquisition Systems

• Electronic Test and Scientific Instrumentation

• Process Control Systems

Description

The HI-674A is a complete 12-bit Analog-to-Digital Converter,
including a +10V reference, clock, three-state outputs and a
digital interface for microprocessor control. Successive
approximation conversion is performed by two monolithic dice
housed in a 28 pin package. The bipolar analog die features
the Harris Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up.

The HI-674A offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The buried zener reference circuit is trimmed for
minimum temperature coefficient.

Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW at ±12V. For MIL-STD-883 compliant
parts, request the HI-674A/883 data sheet.

Pinout

PLASTIC AND SIDEBRAZE DIP

TOP VIEW

+5V SUPPLY, V LOOIC [T
DATA MODE SEL, 12/8 [T

CHIPSEL.CS [T

BYTE ADDR/SHORT rr
CYCLE, Ao LI

READ/CONVERT, RiC |T
CHIP ENABLE, CE [T
+12V/+15V SUPPLY, V cc [7
+10VREF,REFOUT [T

ANALOG rT
COMMON, AC LI

REFERENCE INPUT [jo

-12V/-15V SUPPLY, V EE Q7

BIPOLAR OFFSET rrv
BIP OFF Lli

10V INPUT [13
20V INPUT [14

28] STATUS, STS
2jJ DB11.MSI
26] DB10
25] DBS
24] DBS
23]DB7
22] DBS
21] DB5
20]DB4
1»] DB3
18] DB2
17]DB1
16] DBO, LSB
15] DIG COMMON, DC

DIGITAL
J> DATA
OUTPUTS

Ordering Information

PART

TEMP.

NUMBER

INL

RANGE

PACKAGE

HI3-674AJN-5

±1.0LSB

0°C to +75°C

28 Pin Plastic DIP

HI3-674AKN-5

+0.5LSB

0°C to +75°C

28 Pin Plastic DIP

HI1-674AJD-5

+1.0LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-674AKD-5

10.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-674ALD-5

±0.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-674ASD-2

±1.0LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-674ATD-2

±0.5LSB

■55°Cto+125°C

28 Pin Ceramic DIP

HI1-674AUD-2

+0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-674ASD/883

±1.0LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-674ATD/883

±0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-674AUD/883

±0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI4-674ASE/883

±1.0LSB

-55°Cto+125°C

44 Pin Ceramic LCC

HI4-674ATE/883

±0.5LSB

-55°Cto+125°C

44 Pin Ceramic LCC

HI4-674AUE/883

±0.5LSB

-55°Cto+125°C

44 Pin Ceramic LCC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.e. Handling Procedures.
Copyright © Harris Corporation 1992 1 2g

File Number 3097.1

HI-674A

Functional Block Diagram

BIT OUTPUTS
A

LSB

Aq O-

CE o-

CONTROL
LOGIC

1 M 111 1 1 1 1 M

NIBBLE* A

NIBBLE* B

NIBBLE* C

THREE-STATE BUFFERS AND CONTROL

POWER-UP RESET

OSCILLATOR

] O

J 12 BITS

SAR

DIGITAL CHIP

VrefIN o-

Vr EF OUT o-

ANALOG CHIP

STROBE

+10V
REF.

DAC

\ ^

5k ;

7i H

? 2 5

6 6 6

BIP. 20V 10V
OFF INPUT INPUT

-o V LO oic

DIGITAL
COMMON

-o STS

-»V CC
-o V EE

' "Nibble* is a 4 bit digital word

1-29

Specifications HI-674A

Thermal Information

Absolute Maximum Ratings

Supply Voltage

V cc to Digital Common OV to +16.5V

V EE to Digital Common OV to -16.5V

v logic ,0 Digital Common OV to +7V

Analog Common to Digital Common ±1V

Control Inputs

(CE, CS, Aq, 12/8, R/C) to Digital Common . . . .-0.5V to V LOGlc +0.5V
Analog Inputs

(REFIN, BIPOFF, 10VIN) to Analog Common ±16.5V

20VIN to Analog Common ±24V

REFOUT Indefinite short to Common, momentary short to Vcc

Operating Temperature Range

HI3-674AxN-5, HI1-674AxD-5 0°C to +75°C

HI1-674AXD-2 -55°C to +1 25°C

Junction Temperature

HI3-674AxN-5 +150°C

HI1-674AxD-2, HI1-674AxD-5 +175°C

Storage Temperature Range

HI3-674AXN-5 -40°C < T A < +85°C

HI1-674AxD-2, HI1-674AxD-5 -65°C < T A < +150°C

Lead Temperature (Soldering, 10s) 300°C

CAUTION: Stresses above those listed in -Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections ol this specification is not implied.

HI3-674AXN-5 75°C/W

HI1-674AXD-2, HI1-674AXD-5 48°C/W 15°C/W

Power Dissipation at 75°C (Note 1 )

HI3-674AxN-5 1000mW

HI1-674AXD-2, HI1-674AxD-5 2083mW

Power Dissipation Derating Factor Above +75°C

HI3-674AxN-5 13.3mW7°C

HI1-674AXD-2, HM-674AxD-5 20.8mW/°C

Transistor Count 1117

NOTE:

1. Dissipation rating assumes device is mounted with all leads sol-
dered to printed circuit board.

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG , c = +5V, v EE :

Unless Otherwise Specified

-15V or -12V,

TEMPERATURE RANGE

-5 (0°C to +75°C)

PARAMETERS

HI-674AJ

HI-674AK

HI-674AL

UNITS

Resolution (max)

Bits

Linearity Error
+25°C (Max)
0°C to +75°C (Max)

±1
±1

±1/2
±1/2

LSB
LSB

Differential Linearity Error

+25°C (Max resolution for which no missing codes is guaranteed)
+25°C

T MIN 10 T MAX

±1
12
11

±1
12
12

±1/2
12
12

LSB
Bits
Bits

Unipolar Offset (max)
Adjustable to Zero

±2

±1.5

±1

LSB

Bipolar Offset (max)

V, N = OV (Adjustable to Zero)
V PN = -10V

±4

±0.15

±4
±0.1

±3
±0.1

LSB

% of F.S.

Full Scale Calibration Error

+25°C (Max), with fixed 50C2 resistor from REF OUT to REF IN

(Adjustable to Zero)
t min to T MAX (No adjustment at +25°C)
T M!N to T MAX (With adjustment to zero +25°C)

±0.25

±0.475
±0.22

±0.25

±0.375
0.12

±0.15

±0.20
0.05

% of F.S.

% Of F.S.
% of F.S.

Temperature Coefficients

Guaranteed max change, T M , N to T MAX (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2(10)
±2(10)
±9 (45)

±1(5)
±1(5)
±2(10)

±1 (5)
±1 (5)
±2(10)

LSB (ppnV°C)
LSB (pprrVC)
LSB (ppm/°C)

Power Supply Rejection

Max change in Full Scale Calibration

+1 3.5V < V cc < +1 6.5V or +1 1 .4V < V cc < +1 2.6V

+4.5V < V L0G | C < +5.5V

-16.5V < V EE < -13.5V or -12.6V < V EE < -11.4V

±2
±1/2
±2

±1
±1/2
±1

±1

±1/2
±1

LSB
LSB
LSB

1-30

Specifications HI-674A

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG | C = +sv, v EE = -15V or -12V,

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE

-5 (0°C to +75°C)

PARAMETERS

HI-674AJ

HI-674AK

HI-674AL

UNITS

Analog Inputs
Input Ranges
Bipolar

-5 to +5
-in tn 4.m

- 1 v iu + 1 u

V
V

Unipolar

0to+10
to +20

V
V

Input Impedance
10V Span
20V Span

5K, ±25%
10K,±25%

Q
£1

Power Supplies

Onoratinn X/nltanp Rannp
V LOGIC

Vcc

v EE

+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5

V
V
V

Operating Current
'logic

l oc +15V Supply
l EE -15V Supply

7Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max

mA
mA
mA

Power Dissipation
±15V, +15V
±12V, +5V

51 5 Typ, 720 Max
385 Typ

mW
mW

Internal Reference Voltage
t min to T MAX

Output current, available for external loads (External load should not
change during conversion).

+10.00 ±0.05 Max
2.0 Max

Volts
mA

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v LOG | C - +5V, v EE = -isv or -12V,

Unless Otherwise Specified

TEMPERATURE RANGE

-2(+55°Cto+125 C)

PARAMETERS

HI-674AS

HI-674AT

HI-674AU

UNITS

Resolution (max)

Bits

Linearity Error
+25°C (Max)
0°C to +75°C (Max)

H- H-

±1/2
±1

LSB
LSB

Differential Linearity Error

+25°C (Max resolution for which no missing codes is guaranteed)

+25°C

T MIN ,0 TmaX

±1

12
11

±1
12
12

±1/2
12
12

LSB
Bits
Bits

Unipolar Offset (max)
Adjustable to Zero

±2

±1.5

±1

LSB

Bipolar Offset (max)

V, N = 0V (Adjustable to Zero)
V IN = -10V

±4
±0.15

±4
±0.1

±3
±0.1

LSB
% of F.S.

Full Scale Calibration Error

+25°C (Max), with fixed 50£2 resistor from REF OUT to REF IN

(Adjustable to Zero)
t min t0 t max ( No adjustment at +25°C)
t min 'o t max ( Wi ' n adjustment to zero +25°C)

±0.25

±0.75
±0.50

±0.25

±0.50
0.25

±0.15

±0.275
±0.125

% Of F.S.

% of F.S.
% Of F.S.

1-31

Specifications HI-674A

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V,

Vlogic ■ + 5V, V EE = -15V or -12V,

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE

-2(+55 Cto+125 C)

PARAMETERS

HI-674AS

HI-674AT

HI-674AU

UNITS

Temperature Coefficients

Guaranteed max change, T M | N to T MAX (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2(5)
±2(5)
±20(50)

±1 (2.5)
±2(5)
±10(25)

±1 (2.5)
±1 (2.5)
±5 (12.5)

LSB (ppm/°C)
LSB (ppnVC)

Power Supply Rejection

Max change in Full Scale Calibration

+13.5V < V cc < +16.5V or +1 1.4V < V cc < +12.6V

+4.5V < V LOG | C < +5.5V

-16.5V < V EE < -13.5V or -12.6V < V EE < -11.4V

±2
±1/2
±2

±1
±1/2
±1

LSB
LSB
LSB

Analog Inputs
Input Ranges
Bipolar

-5 to +5
-10 to +10

V
V

Unipolar

to +10
to +20

V
V

Input Impedance
10V Span
20V Span

5k£2, ±25%
10W1, ±25%

a
a

Power Supplies

Operating Voltage Range

V LOGIC

Vcc
Vee

+4.5 to +5.5
+11. 4 to +16.5
-11.4 to -16.5

V
V
V

Operating Current
'logic

Ice +1 5V Supply
l EE -15V Supply

7Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max

mA
mA
mA

Power Dissipation
±15V, +15V
±12V, +5V

515 Typ, 720 Max
385 Typ

mW
mW

Internal Reference Voltage

T MIN t0 T MAX

Output current available for external loads (External load should not
change during conversion).

+10.00 ±0.05 Max
2.0 Max

Volts
mA

Digital Characteristics (Note 1) All Models, Over Full Temperature Range

PARAMETERS

MIN

TYP

MAX

Logic Inputs (CE, CS, R/C, AO, 12/8) (Note 2)

Logic "1"

+2.4V

+5.5V

Logic "0"

-0.5V

+0.8V

Current

-5uA

±0.1 uA

+5uA

Capacitance

5pF

Logic Outputs (DB1 1 -DB0, STS)

Logic "0"(I S | NK - 1.6mA)

+0.4V

Logic "1" (Isource " 500uA)

+2.4V

Leakage (High Z State, DB1 1-DB0 Only)

-5uA

±0.1 uA

+5uA

Capacitance

5pF

NOTES:

1 . See "HI-674A Timing Specifications" for a detailed listing of digital timing parameters.

2. Although this guaranteed threshold is higher than standard TTL (+2.0V), bus loading is much less, i.e., typical input current is only 0.25%
of a TTL load.

Specifications HI-674A

Timing Specifications +25°C, Unless Otherwise Specified

SYMBOL

PARAMETER

MIN

rvP

MAX

UNITS

CONVERT MODE

lose

STS Delay from CE

200

'hEC

CE Pulse Width

CS to CE Setup

l«sc

CS Low During CE High

•sRC

R/C to CE Setup

Ihrc

R/C Low During CE High

'sac

Ao to CE Setup

'hac

Aq Valid During CE High

Conversion Time

12BitCycleT MIN toT M(U <

8BitCycleT MlN toT MAX

READ MODE

•dd

Access Time from CE

150

<hd

Data Valid After CE Low

Ihl

Output Float Delay

100

150

'sSR

CS to CE Setup

'sRR

R/C to CE Setup

'SAR

Aq to CE Setup

•hsr

CS Valid After CE Low

'hrr

R/C High After CE Low

•har

Aq Valid After CE Low

tHS

STS Delay After Data Valid

850

NOTE:

1 . Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kH load.

Definitions of Specifications

Linearity Error

Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through "full scale". The point
used as "zero" occurs V 2 LSB ( 1 .22m V for 1 0V span) before the
first code transition (all zeros to only the LSB "on"). "Full scale"
is defined as a level 1 1 / 2 LSB beyond the last code transition (to
all ones). The deviation of a code from the true straight line is
measured from the middle of each particular code.

The HI-674AK, AL, AT, and AU grades are guaranteed for
maximum nonlinearity of ±V 2 LSB. For these grades, this
means that an analog value which falls exactly in the center
of a given code width will result in the correct digital output
code. Values nearer the upper or lower transition of the code
width may produce the next upper or lower digital output
code. The HI-674AJ and AS grades are guaranteed to
±1LSB max error. For these grades, an analog value which
falls within a given code width will result in either the correct
code for that region or either adjacent one.

Note that the linearity error is not user-adjustable.

Differential Linearity Error (No Missing Codes)

A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing

sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-674AK, AL, AT, and
AU grades, which guarantee no missing codes to 12-bit resolu-
tion, all 4096 codes must be present over the entire operating
temperafure ranges. The HI-674AJ and AS grades guarantee
no missing codes to 11 -bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice very few of the 12-bit codes are missing.

Unipolar Offset

Bipolar Offset

1-33

HI-674A

Full Scale Calibration Error

2 12/8

STS28

HIGH BITS

3CS

24-27

IIDOLE BITS

5 R/C

20-23

LOW BITS

SCE

16-18

10 REF IN

8 REF OUT

12 BIP OFF

+SV1

1310V|h

+15V7

14 20V m *

-15V 11

Q ANA rOU

DIG COM 15

•When driving the 20V (pin 14) input, minimize capacitance on pin 13.

FIGURE 1. UNIPOLAR CONNECTIONS

Temperature Coefficients

The temperature coefficients for full-scale calibration, unipo-
lar offset, and bipolar offset specify the maximum change
from the initial (+25°C) value to the value at T M , N or T MAX .

Power Supply Rejection

The standard specifications for the HI-674A assume use of
+5.00 and ±15.00 or ±12.00 volt supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.

Code Width

±10V

1310V, N
14 20V m *

8 ANA COM DIG COM 15

S O . m SANACOM DIG COM 15 — .

z> v I I '-I

•When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. BIPOLAR CONNECTIONS

Quantization Uncertainty

Analog-to-digital converters exhibit an inherent quantization
uncertainty of ± 1 / 2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.

Left-justified Data

The data format used in the HI-674A is left-justified. This
means that the data represents the analog input as a frac-
tion of full-scale, ranging from to . This implies a
binary point to the left of the MSB.

Applying the HI-674A

PHYSICAL MOUNTING AND LAYOUT CONSIDERATIONS
Layout

1-34

HI-674A

In general, sensitive analog signals should be routed
between ground traces and kept well away from digital lines.
If analog and digital lines must cross, they should do so at
right angles.

Power Supplies

Supply voltages to the HI-674A (+15V, -15V and +5V) must
be "quiet" and well regulated. Voltage spikes on these lines
can affect the converter's accuracy, causing several LSB's to
flicker when a constant input is applied. Digital noise and
spikes from a switching power supply are especially trouble-
some. If switching supplies must be used, outputs should be
carefully filtered to assure "quiet" DC voltage at the con-
verter terminals.

Further, a bypass capacitor pair on each supply voltage ter-
minal is necessary to counter the effect of variations in sup-
ply current. Connect one pair from pin 1 to 15 (V L ogic
supply), one from pin 11 to 9 (V cc to Analog Common) and
one from pin 11 to 9 (V EE to Analog Common). For each
capacitor pair, a 10nF tantalum type in parallel with a 0.1uF
ceramic type is recommended.

Ground Connections

The typical HI-674A ground currents are 6m ADC into pin 9
(Analog Common) and 3m ADC out of pin 15 (Digital Com-
mon). These pins should be tied together at the package to
guarantee specified performance for the converter. In addi-
tion, a wide PC trace should run directly from pin 9 to (usu-
ally) 15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance
from the system's "single point" ground, make only these
connections to pins 9 and 15: Tie them together at the pack-
age, and back to the system ground with a single path. This
path should have low resistance since it will carry about 3mA
of DC current. (Code dependent currents flow in the V cc ,
V EE and V LOG | C terminals, but not through the HI-674A's
Analog Common or Digital Common).

ANALOG SIGNAL SOURCE

The device chosen to drive the HI-674A analog input will see a
nominal load of 5K£1 (10V range) or 10kn (20V range). How-
ever, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in cur-
rent at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 950ns intervals. This requires low out-
put impedance and fast settling by the signal source.

The output impedance of an op amp, for example, has an
open loop value which, in a closed loop, is divided by the
loop gain available at a frequency of interest. The amplifier
should have acceptable loop gain at 1 MHz for use with the
HI-674A. To check whether the output properties of a signal
source are suitable, monitor the 674A's input (pin 13 or 14)
with an oscilloscope while a conversion is in progress. Each
of the twelve disturbances should subside in one half micro-
second or less. (The comparator decision is made about
850ns after each code change from the SAR).

If the application calls for a Sample/Hold to precede the con-
verter, it should be noted that not all Sample/Holds are com-

patible with the HI-674A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Harris HA-5320 Sample/Hold, which was designed for use
with the HI-674A.

RANGE CONNECTIONS AND CALIBRATION
PROCEDURES

The HI-674A is a "complete" A/D converter, meaning it is fully
operational with addition of the power supply voltages, a Start
Convert signal, and a few external components as shown in
Figures 1 and 2. Nothing more is required for most applications.

Whether controlled by a processor or operating in the stand-
alone mode, the HI-674A offers four standard input ranges:
OV to +10V, OV to +20V, ±5V and ±10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been dis-
cussed in an earlier section.

Unipolar Connections and Calibration

Refer to Figure 1. The resistors shown* are for calibration of
offset and gain. If this is not required, replace R2 with a 50ft
1% metal film resistor and remove the network on pin 12.
Connect pin 12 to pin 9. Then, connect the analog signal to
pin 13 for the OV to 10V range, or to pin 14 for the OV to 20V
range. Inputs to +20V (5V over the power supply) are no
problem - the converter operates normally.

Calibration consists of adjusting the converter's most nega-
tive output to its ideal value (offset adjustment), then, adjust-
ing the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in prin-
ciple, one is setting the output with respect to the midpoint of
an increment of analog input, as denoted by two adjacent
code changes. Nominal value of an increment is one LSB.
However, this approach is impractical because nothing "hap-
pens" at a midpoint to indicate that an adjustment is com-
plete. Therefore, calibration is performed in terms of the
observable code changes instead of the midpoint between
code changes.

Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is lV 2 LSB's below the nominal full scale (+9.9963V for
10V range; +1 9.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.

Bipolar Connections and Calibration

1-35

HI-674A

Connect the Analog signal to pin 13 for a ±5V range, or to
pin 1 4 for a ±10V range. Calibration of offset and gain is sim-
ilar to that for the unipolar ranges as discussed above. First
apply a DC input voltage V 2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the +10V
range). Adjust the offset potentiometer R1 for flicker between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage 1 1 / 2 LSB's below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110and 1111 1111 1111.

'The 10012 potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V
(LSB equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more
convenient. For these, replace R2 by a 50£2, 1% metal film
resistor. Then, to provide Gain Adjust for the 10.24V range, add
a 200Q potentiometer in series with pin 13. For the 20.48V
range, add a 500Q potentiometer in series with pin 14.

CONTROLLING THE HI-574A

The HI-674A includes logic for direct interface to most micro-
processor systems. The processor may take full control of
each conversion, or the converter may operate in the "stand-
alone" mode, controlled only by the R/C input. Full control
consists of selecting an 8 or 12 bit conversion cycle, initiating
the conversion, and reading the output data when ready-
choosing either 12 bits at once or 8 followed by 4, in a left-
justified format. The five control inputs are all TTL/CMOS-
compatible: (12/8, CS, Aq, R/C and CE). Table 1 illustrates
the use of these inputs in controlling the converter's opera-
tions. Also, a simplified schematic of the internal control logic
is shown in Figure 3.

"Stand-Alone Operation"

The simplest_control interface calls for a singe control line con-
nected to R/C. Also, CE and 12/8 are wired high, CS and Aq are
wired low, and the output data appears in words of 12 bits each.

STAND-ALONE MODE TIMING

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

•hrl

Low R/C Pulse Width

tos

STS Delay from R/C

200

•hdh

Data Valid after R/C Low

•hs

STS Delay after Data Valid

850

•hrh

High R/C Pulse Width

150

( DDR

Data Access Time

150

Time is measured from 50% level of digital transitions. Tested with a
50pF and 3k£l load.

Conversion Length

A Convert Start transition (see Table 1 ) latches the state of
Aq, which determines whether the conversion continues for
12 bits (Aq low) or stops with 8 bits (Aq high). If all 12 bits
are read following an 8 bit conversion, the three LSB's will
read zero and DB3 will read ONE. Aq is latched because it is

INPUT BUFFERS

12/8

READ CONTROL

rP>7L>

] =E£>

Aq LATCH

CONTROL

NIBBLE B ZERO
' OVERRIDE

NIBBLE A, B

► NIBBLE C

IrF

CURRENT ■+ STROBE
CONTROLLED
OSCILLATOR ■+ CLOCK

RESET

EOC13

FIGURE 3. HI-674A CONTROL LOGIC

1-36

HI-674A

•hrl

R/C

FIGURE 4. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION

r/c

"dob

'HDfi

DB11-DB0 HIGH-Z

/ DATA \

HIGH-Z

FIGURE 5. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z

also involved in enabling the output buffers (see "Reading
the Output Data"). No other control inputs are latched.

TABLE 1. TRUTH TABLE FOR HI-574A CONTROL INPUTS

R/C

12A)

OPERATION

None

Initiate 12 bit conversion

Initiate 8 bit conversion

Initiate 1 2 bit conversion

Initiate 8 bit conversion

Initiate 12 bit conversion

Initiate 8 bit conversion

Enable 12 bit Output

Enable 8 MSB's Only

Enable 4 LSB's Plus 4 Trailing
Zeroes

Conversion Start

A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so

This variety of HI-674A control modes allows a simple inter-
face in most system applications. The Convert Start timing
relationships are illustrated in Figure 6.

Reading the Output Data

The output data buffers remain^ in a high impedance state
unt il four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and Ao. Timing constraints are illus-
trated in Figure 7.

1-37

HI-674A

The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatib!e. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12 or 16 bit data bus. The Aq input is ignored.

With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Aq. This allows an 8 bit data bus to
be connected as shown in Figure 8. Aq is usually tied to the
least significant bit of the address bus, for storing the
HI-674A output in two consecutive memory locations. (With
Aq low, the 8 MSB's only are enabled. With Aq high, 4MSB's
are disabled, bits 4 through 7 are forced to zero, and the
4 LSB's are enabled). This two byte format is considered "left
justified data", for which a decimal (or binary!) point is
assumed to the left of byte 1:

BYTE 1

BYTE 2

x [ x | x | x"[~x" | X | X

MSB

LSB

A read operation usually begins after the conversion is com-
plete and STS is low. For earliest access to the data how-
ever, the read should begin no later than (t D0 + t H s) before
STS goes low. See Figure 7.

<ssc —

<SRC

•hrc -

•sac »-|

'hac

STS

DB11-DB0

'DSC

- 'hsc

X3E

HIGH IMPEDANCE

CE-

es-

R/C
Ao-

STS -

-<SRR

•hah "

HIGH IMPEDANCE

too

DATA
"VALID"

<HO

3_h

<HL

FIGURE 7. READ CYCLE TIMING

FIGURE 8. INTERFACE TO AN 8 BIT DATA BUS

FIGURE 6. CONVERT START TIMING

1-38

SEMICONDUCTO

HI-774

July 1992

8lis, Complete 12-Bit A/D Converter
with Microprocessor Interface

Features

• Complete 12-Bit A/D Converter with Reference and
Clock

• Digital Error Correction

• Full 8-, 12- or 16-Bit Microprocessor Bus Interface

• 150ns Bus Access Time

• No Missing Codes Over Temperature

• Minimal Setup Time for Control Signals

• %s Maximum Conversion Time Over Temperature

• Low Noise, via Current-Mode Signal Transmission
Between Chips

• Byte Enable/Short Cycle (A Q Input)

- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
the Start Convert Input (To Set the Conversion Length)

• Faster Version of the HI-574A and HI-674A

• Same Pinout as the HI-574A and HI-674A

• ±12V to ±15V Operation

Applications

• Industrial Data Acquisition Systems

• Electronic Test and Scientific Instrumentation

• Process Control Systems

Description

The HI-774 is a complete 12-bit Analog-to-Digital Converter,
including a +10V reference clock, three-state outputs and a
digital interface for microprocessor control. Successive
approximation conversion is performed by two monolithic
dice housed in a 28 pin package. The bipolar analog die fea-
tures the Harris Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up. The
digital die features the Smart SAR (SSAR™), which includes
a digital error correction circuit.

The HI-774 offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.

Power requirements are +5V and ±12V to +15V, with typical
dissipation of 390m W at ±12V. For MIL-STD-883 compliant
parts, request the HI-774A/883 data sheet.

Pinout

PLASTIC AND SIDEBRAZE DIP

TOP VIEW

+5V SUPPLY, V LO gic [7
DATA MODE SEL, 12/B [T

CHIPSEL.CS [T

BYTE ADDR/SHORT fT
CYCLE, Ao LI

READ/CONVERT, fVC \T

CHIP ENABLE, CE [T

+12V7+15V SUPPLY, V cc [T

+10V REF, REF OUT [T

ANALOG rr-
COMMON.AC LI

REFERENCE WPUT [jo

-12V/-15V SUPPLY, V E [iT

BIPOLAR OFFSET rfi
BIPOFF Ll£

10V INPUT [13
20V INPUT \u

28] STATUS, STS
27] DB11, MSB
26] DB10
25] DB9
24] DBS
23] DB7
22] DB6
2l]DB5
20] DB4
Ta| DB3
W] DB2
17]t>B1

«] DBO, LSB
15] DIG COMMON, DC

DIGITAL
^ DATA
OUTPUTS

Ordering Information

PART

TEMP.

NUMBER

INL

RANGE

PACKAGE

HI3-774JN-5

±1 .0LSB

0°C to +75°C

28 Pin Plastic DIP

HI3-774KN-5

±0.5LSB

0°C to +75°C

28 Pin Plastic DIP

HI1-774JD-5

±1.0LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-774KD-5

±0.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-774LD-5

±0.5LSB

0°C to +75°C

28 Pin Ceramic DIP

HI1-774SD-2

±1.0LSB

-55°CtO+125°C

28 Pin Ceramic DIP

HI1-774TD-2

±0.5LSB

-55°C to +125°C

28 Pin Ceramic DIP

HI1-774UD-2

10.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-774S/883

±1.0LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-774T/883

+0.5LSB

-55°Cto+125°C

28 Pin Ceramic DIP

HI1-774U/883

±0.5LSB

-55°C to+125°C

28 Pin Ceramic DIP

HI4-774S/883

±1.0LSB

-55°C to+125°C

44 Pin Ceramic LCC

HI4-774T/883

±0.5LSB

-55°C to+125°C

44 Pin Ceramic LCC

HI4-774U/883

+0.5LSB

-55°C to+125°C

44 Pin Ceramic LCC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper US. Handling Procedures.
Copyright © Harris Corporation 1992

File Number 3098.1

HI-774

Functional Block Diagram

BIT OUTPUTS
A

MSB

9 9 9 9

A<jO-
WC o-

CE o-

LOGIC

LSB

B O O • O i i

NIBBLE* A

NIBBLE* B

NIBBLE* C

THREE-STATE BUFFERS AND CONTROL

OSCILLATOR

^jl2BITS^

DIGITAL CHIP

VrefIN <
VreF OUT <

ANALOG CHIP

1 2 BITS

STROBE

+10V
REF.

DAC

ANALOG
COMMON

BIP. 20V 10V
OFF INPUT INPUT

I v LOGIC
. DIGITAL

, STS

-o V cc
-o V EE

•■Nibble" is a 4 bit digital word

1-40

Specifications HI-774

Thermal Information

75°C/W
48°C/W

15°C/W

Absolute Maximum Ratings

Supply Voltage

V cc to Digital Common OV to +16.5V

V EE to Digital Common OV to -16.5V

V L0 Gic 'o Digital Common OV to +7V

Analog Common to Digital Common ±1V

Control Inputs

(CE, CS, Ao, 12/8, R/C) to Digital Common .... -0.5V to V LOG , C +0.5V
Analog Inputs

(REFIN, BIPOFF, 10V, N ) to Analog Common +16.5V

20V, N to Analog Common ±24V

REFOUT Indefinite short to Common, momentary short to Vcc

Operating Temperature Range

HI3-774xN-5, H1 1 -774xD-5 0°C to +75°C

HI 1-774x0-2 -55°C to +125°C

Junction Temperature

HI3-774XN-5 +150°C

HI1-774xD-2, HI1-774XD-5 +175°C

Storage Temperature Range

HI3-774xN-5 -40°C < T A < +85°C

HI1-774xD-2, HI1-774xD-5 -65°C < T A < +150°C

Lead Temperature (Soldering, 10s) 300°C

CAUTION: Stresses above those listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specilication is not implied.

Thermal Resistance

HI3-774XN-5

HI1-774XD-2, HI1-774XD-5

Power Dissipation at 75°C (Note 1 )

HI3-774XN-5 1000mW

HI1-774XD-2, HI1-774XD-5 2083mW

Power Dissipation Derating Factor Above +75°C

HI3-774XN-5 13.3mW/°C

HI1-774XD-2, HI1-774XD-5 20.8mW/°C

Transistor Count 2117

NOTE:

1. Dissipation rating assumes device is mounted with all leads sol-

dered to printed circuit board.

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +isv or +12V, v L0GIC = +5V, v EE = -isv or -12V,

Unless Otherwise Specified

TEMPERATURE RANGE

-5 (0°C to +75°C)

PARAMETERS

HI-774J

HI-774K

HI-774L

UNITS

Resolution (max)

Bits

Linearity Error

+25°C (Max)

±1

±1/2

LSB

0°C to +75°C (Max)

±1

±1/2

LSB

Max resolution for which no missing codes is guaranteed

+25°C

Bits

T MIN t0 T MAX

Bits

Unipolar Offset (max)

Adjustable to Zero

±1.5

±1

LSB

Bipolar Offset (max)

v in = ov (Adjustable to Zero)

±4

±3

LSB

V, N = -10V

±0.15

±0.1

% of F.S.

Full Scale Calibration Error

+25-C (Max), with fixed 50n resistor from REF OUT to REF IN

±0.25

±0.15

% of F.S.

(Adjustable to Zero)

t min to t max ( No adjustment at +25°C)

±0.475

±0.375

±0.20

% Of F.S.

t min ,0 T MAX (With adjustment to zero +25°C)

±0.22

0.12

0.05

% of F.S.

Temperature Coefficients

Guaranteed max change, T M[N to T MAX (Using internal reference)

Unipolar Offset

±2

±1

LSB

Bipolar Offset

±2

±1

LSB

Full Scale Calibration

±9

±5

±2

LSB

Power Supply Rejection

Max change in Full Scale Calibration

+1 3.5V < V cc < +1 6.5V or +1 1 .4V < V cc < +1 2.6V

±2

±1

LSB

+4.5V < V L0G ic < +5.5V

±1/2

LSB

-16.5V < V EE < -13.5V or -12.6V < V EE < -1 1.4V

±2

±1

LSB

Analog Inputs

Input Ranges

-5 to +5

-10 to +10

1-41

Specifications HI-774

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V of +12V, v LOG | C = +sv, v EE = -isv or -12V,

Unless Otherwise Specified (Continued)

TEMPERATURE RANGE

-5 (0°C to +75°C)

PARAMETERS

HI-774J

HI-774K

HI-774L

UNITS

Input Ranges (Continued)
Unipolar

to +10
to +20

V
V

Input Impedance
10V Span
20V Span

5K, ±25%
10K, ±25%

a
a

Power Supplies

Operating Voltage Range

V LOGIC

Vcc

+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5

V
V
V

Operating Current
'logic

l cc +15V Supply
l EE -15V Supply

7Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max

mA
mA
mA

Power Dissipation
±15V, +15V
±12V, +5V

51 5 Typ, 720 Max
385 Typ

mW
mW

Internal Reference Voltage
t min to T MAX

Output current, available for external loads (External load should not
change during conversion).

+10.00 ±0.05 Max
2.0 Max

Volts
mA

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v L0G , c = +sv, v EE = -isv or -12V,

Unless Otherwise Specified

TEMPERATURE RANGE

-2(+55°Cto+125 <> C)

PARAMETERS

H1-774S

HI-774T

HI-774U

UNITS

Resolution (max)

Bits

Linearity Error
+25°C (Max)
0°C to +75°C (Max)

±1
±1

±1/2
±1

LSB
LSB

Max resolution for which no missing codes is guaranteed

+25°C

T MIN ,0 T MAX

11
11

12
12

Bits
Bits

Unipolar Offset (max)
Adjustable to Zero

±2

±1

LSB

Bipolar Offset (max)

V| N = 0V (Adjustable to Zero)
V IN = -10V

±4
±0.15

±4
±0.1

±3
±0.1

LSB
%0fF.S.

Full Scale Calibration Error

+25°C (Max), with fixed 50Q resistor from REF OUT to REF IN

(Adjustable to Zero)
t min t° t max (No adjustment at +25°C)
Tmin to T"max ( wi,n adjustment to zero +25°C)

±0.25

±0.75
±0.50

±0.25

±0.50
0.25

±0.15

±0.275
±0.125

% Of F.S.

% Of F.S.
% of F.S.

Temperature Coefficients

Guaranteed max change, T Mm to T MAX (Using internal reference)
Unipolar Offset
Bipolar Offset
Full Scale Calibration

±2
±2
±20

±1
±2
±10

±1
±1
±5

LSB
LSB
LSB

Power Supply Rejection

Max change in Full Scale Calibration

+13.5V < V cc < +16.5V or +1 1.4V < V cc < +12.6V

+4.5V < V L0G | C < +5.5V

-16.5V < V EE < -13.5V or -12.6V < V EE < -11.4V

±2
±1/2
±2

±1
±1/2
±1

LSB
LSB
LSB

1-42

Specifications HI-774

DC and Transfer Accuracy Specifications Typical at +25°c with v cc = +15V or +12V, v L0GIC = +5V v EE = -15V or -12V,

Unless Otherwise Specified (Continued)

rrAinrnNTiinr r~v a h i /~* r*

TEMPERATURE RANGE

PARAMETERS

HI-774S | H1-774T | HI-774U

UNITS

Analog Inputs

Input Ranges

Bipolar

-5 to +5

- 1 U 10 + 1 u

w
V

Unipolar

0to+10

to +20

Input Impedance

10V Span

5kfi, ±25%

20V Span

10kn. ±25%

Power Supplies

Operating Voltage Range

Vlogic

+4.5 to +5.5

Vcc

+11.410 +16.5

V EE

-11.4 to -16.5

Operating Current

'logic

7 Typ, 1 5 Max

l co +15V Supply

11Typ, 15 Max

l EE -15V Supply

21 Typ, 28 Max

Power Dissipation

±15V, +15V

515 Typ, 720 Max

±12V, +5V

385 Typ

Internal Reference Voltage

T MIN ,0 T MAX

+10.00 ±0.05 Max

Volts

Output current available for external loads (External load should not

2.0 Max

change during conversion).

Digital Specifications All Models, Over Full Temperature Range

PARAMETERS

MIN

TYP

MAX

Logic Inputs (CE, CS, R/C, Aq, 412/8)

Logic "1"

+2.4V

+5.5V

Logic "0"

-0.5V

+0.8V

Current

±0.1 (iA

±5(iA

Capacitance

5pF

Logic Outputs (DB11-DB0, STS)

Logic "0"(I S | NK - 1.6mA)

+0.4V

Logic "1" Osource - 500jiA)

+2.4V

Logic "1" (Isource - 10uA)

+4.5V

Leakage (High Z State, DB1 1-DB0 Only)

±0.1 nA

±5nA

Capacitance

5pF

Timing Specifications +25°C, Unless Otherwise Specified, Into a load with R L = 3k£2 and C L = 50pF

SYMBOL

PARAMETER

MIN TYP

MAX UNITS

CONVERT MODE

'dsc

STS Delay from CE

100

200

'hec

CE Pulse Width

'ssc

CS to CE Setup

•hsc

CS Low During CE High

'SRC

R/C to CE Setup

'hrc

R/C Low During CE High

'sac

Aq to CE Setup

•hac

Aq Valid During CE High

1-43

HI-774

Timing Specifications +25°C, Unless Otherwise Specified, Into a load with R L = 3kn and C L = 50pF (Continued)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

Conversion Time

12BitCycleT MIN toT MAX (-5)

8.0

8BitCycleT MIN toT MAX (-5)

6.4

6.8

12BitCycleT MlN toT MAX (-2)

8BitCycleT MIN toT MAX (-2)

6.8

8.3

READ MODE

loo

Access Time from CE

150

^HD

Data Valid After CE Low

t H L

Output Float Delay

150

•sSR

CS to CE Setup

*SRR

R/C to CE Setup

'SAH

Aq to CE Setup

>HSR

CS Valid After CE Low

'hrr

R/C High After CE Low

•har

Aq Valid After CE Low

•hs

STS Delay After Data Valid

300

NOTE:

1 . Time is measured from 50% level of digital transitions, except High Z output conditions which are measured at the 1 0% or 90% point.

Definitions of Specifications

Linearity Error

Linearity error refers to the deviation of each individual code
from a line drawn from "zero" through lull scale". The point
used as "zero" occurs 1 / 2 LSB (1 ,22mV for 1 0V span) before the
first code transition (all zeros to only the LSB "on"). "Full scale"
is defined as a level 1 1 / 2 LSB beyond the last code transition (to
all ones). The deviation of a code from the true straight line is
measured from the middle of each particular code.

The HI-774K and L grades are guaranteed for maximum non-
linearity of ±V 2 LSB. For these grades, this means that an ana-
log value which falls exactly in the center of a given code
width will result in the correct digital output code. Values
nearer the upper or lower transition of the code width may pro-
duce the next upper or lower digital output code. The HI-774J
is guaranteed to ±1 LSB max error. For this grade, an analog
value which falls within a given code width will result in either
the correct code for that region or either adjacent one.

Note that the linearity error is not user-adjustable.

Differential Linearity Error (No Missing Codes)

A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increasing
sequence as the analog input level is increased. Thus every
code must have a finite width. For the HI-774K and L grades,
which guarantee no missing codes to 12-bit resolution, all
4096 codes must be present over the entire operating temper-
ature ranges. The HI-774J grade guarantees no missing
codes to 11 -bit resolution over temperature; this means that
all code combinations of the upper 11 bits must be present; in
practice very few of the 12-bit codes are missing.

Unipolar Offset

The first transition should occur at a level V 2 LSB above analog
common. Unipolar offset is defined as the deviation of the

actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset tempera-
ture coefficient specifies the maximum change of the transition
point over temperature, with or without external adjustment.

Bipolar Offset

Similarly, in the bipolar mode, the major carry transition
(0111 1111 1111 to 1000 0000 0000) should occur for an ana-
log value V 2 LSB below analog common. The bipolar offset
error and temperature coefficient specify the initial deviation
and maximum change in the error over temperature.

Full Scale Calibration Error

The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1 / 2 LSB below the nominal
full scale (9.9963V for 10.000V full scale). The full scale cali-
bration error is the deviation of the actual level at the last
transition from the ideal level. This error, which is typically
0.05 to 0.1% of full scale, can be trimmed out as shown in
Figures 2 and 3. The full scale calibration error over temper-
ature is given with and without the initial error trimmed out.
The temperature coefficients for each grade indicate the
maximum change in the full scale gain from the initial value
using the internal 10V reference.

Temperature Coefficients

The temperature coefficients for full-scale calibration, unipo-
lar offset, and bipolar offset specify the maximum change
from the initial (+25°C) value to the value at T M | N or T MAX .

Power Supply Rejection

The standard specifications for the HI-774 assume use of
+5.00 and ±15.00 or ±12.00 volt supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in

1-44

Hl-774

a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.

Code Width

Quantization Uncertainty

Left-justified Data

The data format used in the Hl-774 is left-justified. This
means that the data represents the analog input as a frac-
tion of full-scale, ranging from to «ggj . This implies a
binary point to the left of the MSB. 4096

Applying the Hl-774

PHYSICAL MOUNTING AND LAYOUT CONSIDERATIONS
Layout

The recommended construction is a double-sided printed cir-
cuit board with a ground plane on the component side. Other
techniques, such as wire-wrapping or point-to-point wiring on
vectorboard, will have an unpredictable effect on accuracy.

In general, sensitive analog signals should be routed
between ground traces and kept well away from digital lines.
If analog and digital lines must cross, they should do so at
right angles.

Power Supplies

Supply voltages to the Hl-774 (+15V, -15V and +5V) must be
"quiet" and well regulated. Voltage spikes on these lines can
affect the converter's accuracy, causing several LSBs to
flicker when a constant input is applied. Digital noise and
spikes from a switching power supply are especially trouble-
some. If switching supplies must be used, outputs should be
carefully filtered to assure "quiet" DC voltage at the con-
verter terminals.

Further, a bypass capacitor pair on each supply voltage ter-
minal is necessary to counter the effect of variations in sup-

ply current. Connect one pair from pin 1 to 15 (V LOG | C
supply), one from pin 7 to 9 (V cc to Analog Common) and
one from pin 11 to 9 (V EE to Analog Common). For each
capacitor pair, a 10uF tantalum type in parallel with a 0.1 uF
ceramic type is recommended.

Ground Connections

The typical Hl-774 ground currents are 6mADC into pin 9
(Analog Common) and 3m ADC out of pin 15 (Digital Com-
mon). These pins should be tied together at the package to
guarantee specified performance for the converter. In addi-
tion, a wide PC trace should run directly from pin 9 to (usu-
ally) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance
from the system's "single point" ground, make only these
connections to pins 9 and 15: Tie them together at the pack-
age, and back to the system ground with a single path. This
path should have low resistance since it will carry about 3mA
of DC current. (Code dependent currents flow in the V cc ,
V EE and V L0GIC terminals, but not through the Hl-774's
Analog Common or Digital Common).

ANALOG SIGNAL SOURCE

The device driving the Hl-774 analog input will see a nominal
bad of 5KO (10V range) or 10ki2 (20V range). However, the
other end of these input resistors may change as much as
±400mV with each bit decision. These input disturbances are
caused by the internal DAC changing codes which causes a
glitch on the summing junction. This creates abrupt changes in
current at the analog input causing a "kick back" glitch from the
input. Because the algorithm starts with the MSB, the first
glitches will be the largest and get smaller as the conversion
proceeds. These glitches can occur at 350ns intervals so an op
amp with a low output impedance and fast settling is desir-
able. Ultimately the input must settle to within the window of
Figure 1 at the bit decision points in order to achieve 12 bit
accuracy.

The Hl-774 differs from the most high-speed successive
approximation type ADC's in that it does not require a high
performance buffer or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8u,s. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input "kick back" disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the "kick back" disturbances must
remain in the Figure 1 window.

If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low out-
put impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Harris HA-5330 or
HA-5320 are recommended.

In any design the input (pin 13 or 14) should be checked dur-
ing a conversion to make sure that the input stays within the
correctable window of Figure 1 .

1-45

HI-774

DIGITAL ERROR CORRECTION

The HI-774 features the smart successive approximation
register (SSAR ™) which includes digital error correction.
This has the advantage of allowing the initial input to vary
within a +31 to -32LSB window about the final value. The
input can move during the first 4.8ns, after which it must
remain stable within ±V 2 LSB. With this feature a conversion
can stan: before the input has settled completely; however, it
must be within the window as described in Figure 1.

The conversion cycle starts by making the first 8-bit deci-
sions very quickly, allowing the internal DAC to settle only to
8-bit accuracy. Then the converter goes through two error
correction cycles. At this point the input must be stable within
±V 2 LSB. These cycles correct the 8-bit word to 12-bit accu-
racy for any errors made (up to +16 or -32 bits). This is up

one count or down two counts at 8-bit resolution. The con-
verter then continues to make the 4LSB decisions, settling
out to 12-bit accuracy. The last four bits can adjust the code
in the positive direction by up to 15 bits. This results in a total
correction range of +31 to -32 bits. When an 8-bit conversion
is performed, the input must settle to within ±V 2 LSB at 8 bit
resolution (which equals ±8 bits at 12-bit resolution).

With the HI-774 a conversion can be initiated before the
input has completely settled, as long as it meets the con-
straints of the Figure 1 window. This allows the user to start
conversion up to 4.8ns earlier than with a typical analog to
digital converter. A typical successive approximation type
ADC must have a constant input during a conversion
because once a bit decision is made it is locked in and can-
not change.

ALLOWABLE INPUT CHANGE
(LSBs AT 12 BIT RESOLUTION)

■ B BIT CONVERSION

BIT DECISION POINTS

± 1 / 2 LSB
L

/.^■"-- I ACT Rl'

MSB BIT DECISION
- 650ns

LAST BIT END OF

DECISION CONVERSION
(12 BIT) (12 BIT)

■12 BIT CONVERSION

1 2
CONVERSION INITIATED

3 4 5
TIME(n.)

FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs. TIME

2 12/8

STS28

3 CS

HIGH BITS

24-27

4 Ao MIDDLE BITS

5 R/C

20-23

LOW BITS

6 CE

16-18

10 REFIN

8 REF OUT

12 BIP OFF

+5V 1

13 10V, N

+15V 7

14 20V, N -

-1SV 11

• ANA DIG COM 15

COM

100Q

±SV

ANALOG °-
INPUTS „

±10V

• | O i • 8 ANA DIG COM 15 _0 —

2 12/8

3 CS

* Ao

5 R/C

6 CE

STS28
HIGH BITS
24-27

MIDDLE BITS
20-23

LOW BITS
16-18

10 REFIN

8 REF OUT

12 BIP OFF

+5V 1

13 10V M

+15V 7

14 20V M *

-15V 11

8 ANA DIG COM 15

COM

•When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. UNIPOLAR CONNECTIONS FIGURE 3. BIPOLAR CONNECTIONS

1-46

HI-774

RANGE CONNECTIONS AND CALIBRATION
PROCEDURES

The HI-774 is a "complete" A/D converter, meaning it is fully
operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figures 2 and 3. Nothing more is required for most
applications.

Whether controlled by a processor or operating in the stand-
alone mode, the HI-774 offers four standard input ranges: OV
to +10V, OV to +20V, ±5V and ±10V. The maximum errors for
gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been dis-
cussed in an earlier section.

Unipolar Connections and Calibration

Refer to Figure 2. The resistors shown* are for calibration of
offset and gain. If this is not required, replace R2 with a 50Q,
1% metal film resistor and remove the network on pin 12.
Connect pin 12 to pin 9. Then, connect the analog signal to
pin 1 3 for the OV to 1 0V range, or to pin 1 4 for the OV to 20V
range. Inputs to +20V (5V over the power supply) are no
problem - the converter operates normally.

For example, midpoint of the first LSB increment should be
positioned at the origin, with an output code of all 0's. To do
this, apply an input of +V 2 LSB (+1.22mV for the 10V range;
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between 0000 0000
0000 and 0000 0000 0001.

Next, perform a Gain Adjust at positive full scale. Again, the
ideal input corresponding to the last code change is applied.
This is 1 1 / 2 LSB's below the nominal full scale (+9.9963V for
10V range; +1 9.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.

Bipolar Connections and Calibration

Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiometers
R1 and R2*. If this isn't required, either or both pots may be
replaced by a 50Q, 1 % metal film resistor.

Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is sim-
ilar to that for the unipolar ranges as discussed above. First

apply a DC input voltage V 2 LSB above negative full scale
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between
output codes 0000 0000 0000 and 0000 0000 0001. Next,
apply a DC input voltage lV 2 LSB's below positive full scale
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110and 1111 1111 1111.

•The 100Q potentiometer R2 provides Gain Adjust for the 10V and
20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 5041, 1 % metal film resistor. Then, to pro-
vide Gain Adjust for the 10.24V range, add a 200n potentiometer in
series with pin 13. For the 20.48V range, add a 500fl potentiometer
in series with pin 14.

Controlling the HI-774

The HI-774 includes logic for direct interface to most micro-
processor systems. The processor may take full control of
each conversion, or the converter may operate in the "stand-
alone" mode, controlled only by the R/C input. Full control
consists of selecting an 8 or 12 bit conversion cycle, initiating
the conversion, and reading the output data when ready-
choosing either 12 bits at once or 8 followed by 4, in a left-
justified format. The five control inputs are all TTL/CMOS-
compatible: (12/8, CS, Aq, R/C and CE). Table 1 illustrates
the use of these inputs in controlling the converter's opera-
tions. Also, a simplified schematic of the internal control logic
is shown in Figure 4.

"Stand-Alone Operation"

The simplest control interface calls_for a singe controj line
connected to R/C. Also, CE and 12/8 are wired high, CS and
Aq are wired low, and the output data appears in words of
12 bits each.

The R/C signal may have any duty cycle within (and includ-
ing) the extremes shown in Figures 5 and 6. In general, data
may be read when R/C is high unless STS is also high, indi-
cating a conversion is in progress. Timing parameters partic-
ular to this mode of operation are listed below under "Stand-
Alone Mode Timing".

STAND-ALONE MODE TIMING

SYMBOL

PARAMETER

MIN

TYP

MAX

UNITS

•hrl

Low R/C Pulse Width

'ds

STS Delay from R/C

200

•hdr

Data Valid after FVC Low

•hs

STS Delay after Data Valid

850

•hrh

High R/C Pulse Width

150

•dDR

Data Access Time

150

1-47

HI-774

INPUT

EH>

EH>~
EH>

I>=0

n5>

READ CONTROL

NIBBLE B ZERO
' OVERRIDE

A.B

EOC9

CK_

Ao LATCH

CURRENT ♦ STROBE
CONTROLLED
OSCILLATOR ♦ CLOCK

| POWER UP
RESET

EOC13

FIGURE 4. HI-774 CONTROL LOGIC

R/C

STS

tHHL

<ds

•c

[*— tHOB

<HS

DB11-DB0

DATA
VAUD

FIGURE 5. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION

R/C

STS

—

'hrh

<D3

«C

•dob

»HDB

DATA \
VALID f

HIGH-Z

FIGURE 6. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z

1-48

HI-774

Conversion Length

A Convert Start transition (see Table 1) latches the state of
Aq, which determines whether the conversion continues for
12 bits (Aq low) or stops with 8 bits (Aq high). If all 12 bits are
read following an 8 bit conversion, the last three LSB's will
read ZERO and DB3 will read ONE. Aq is latched because it
is also involved in enabling the output buffers (see "Reading
the Output Data"). No other control inputs are latched.

TABLE 1. TRUTH TABLE FOB HI-774 CONTROL INPUTS

12*

OPERATION

None

Initiate 12 bit conversion

Initiate 8 bit conversion

Initiate 12 bit conversion

Initiate 8 bit conversion

Initiate 12 bit conversion

Initiate 8 bit conversion

Enable 12 bit Output

Enable 8 MSB's Only

Enable 4 LSB's Plus 4 Trailing
Zeroes

Conversion Start

A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of

the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. To assure that a
particular input controls the start of conversion, the other two
should be set up at least 50ns earlier, however. See the
HI-774 Timing Specifications, Convert mode.

This variety of HI-774 control modes allows a simple inter-
face in most system applications. The Convert Start timing
relationships are illustrated in Figure 7.

Reading the Output Data

The output data buffers remain_ in a high impedance state
unt il four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
the state of inputs 12/8 and Aq. Timing constraints are illus-
trated in Figure 8.

With 12/8 low, the output is organized in two 8 bit bytes,
selected one at a time by Aq- This allows an 8 bit data bus to
be connected as shown in Figure 9. Aq is usually tied to the
least significant bit of the address bus, for storing the HI-774
output in two consecutive memory locations. (With Aq low,
the 8 MSB's only are enabled. With Aq high, 4MSB's are dis-
abled, bits 4 through 7 are forced low, and the 4LSB's are

R/C

tssc-

'SRC

<HRC -

'SAC-

'hac — »-

STS

DB11-DB0

'DSC

>HEC

■ 'kSC

HIGH IMPEDANCE

CE -
CS-

R/C

Ao-

- >SAR <HAR -

"X-

•hs ■

HIGH IMPEDANCE
«DD

DATA
"VALID"

<HL

FIGURE 7. CONVERT START TIMING

See HI-774 Timing Specifications for more

FIGURE 8. READ CYCLE TIMING

1-49

HI-774

enabled). This two byte format is considered "left justified
data", for which a decimal (or binary!) point is assumed to
the left of byte 1:

BYTE 1

MSB

BYTE 2

x|x

XXX

ran

between the two data bytes, which assures that the outputs
strapped together in Figure 9 will never be enabled at the
same time.

A read operation usually begins after the conversion is com-
plete and STS is low. For earliest access to the data how-
ever, the read should begin no later than (t DD + t HS ) before
STS goes low. See Figure 8.

Further, Aq may be toggled at any time without damage to
the converter. Break-before-make action is guaranteed

FIGURE 9. INTERFACE TO AN 8 BIT DATA BUS

1-50

m HARRIS

KMJ SEMICONDUCTOR

HI-5700

July 1992

8-Bit, 20 MSPS Flash A/D Converter

Features

• 20MSPS with No Missing Codes

• 18MHz Full Power Input Bandwidth

• No Missing Codes Over Temperature

• Sample and Hold Not Required

• Single +5V Supply Voltage

• CMOS/TTL

• Overflow Bit

• Improved Replacement for MP7684
Applications

• Video Digitizing

• Radar Systems

• Medical Imaging

• Communication Systems

• High Speed Data Acquisition Systems

Description

The HI-5700 is a monolithic, 8 bit, CMOS Flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 20MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5700 delivers ±0.5LSB dif-
ferential nonlinearity while consuming only 725mW (typical)
at 20MSPS. Microprocessor compatible data output latches
are provided which present valid data to the output bus 1 .5
clock cycles after the convert command is received. An
overflow bit is provided to allow the series connection of two
converters to achieve 9 bit resolution.

The HI-5700 is available in Commercial and Industrial
temperature ranges and is supplied in 28 pin Plastic DIP and
SOIC packages.

Pinout

28 PLASTIC DIP AND SOIC

TOP VIEW

CLK [T

28]V IN

(MSB) D7 [7

27]V REF .

D6[3

EJAVdd

D5[T

25] AGND

D4|T

24] AGND

IMRfT

UAVdd

Vdo[T

22]1/2R

GND [T

SJAVdd

3/4R[j

20] AGND

D3fj0

19] AGND

D2 |lT

igAVDD

(LSB) D1 FT

17]V REF .

16]CET

OVFfTf

1S]CE2

Ordering Information

PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

HI3-5700J-5

0°C to +75°C

28 Pin Plastic DIP

HI9P5700J-5

0°C to +75°C

28 Pin SOIC

HI3-5700A-9

-40°C to +85°C

28 Pin Plastic DIP

HI9P5700A-9

-40°C to +85°C

28 Pin SOIC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1 992

File Number 3174.2

HI-5700

Specifications HI-5700

Absolute Maximum Ratings

Supply Voltage, V 00 to GND (GND - 0.5) < V D0 < +7.0V

Analog and Reference Input Pins. . . . (Vss - 0.5) < V| NA < QJoo +0-5V)

Digital I/O Pins (GND - 0.5) < V ro < (V DD +0.5V)

Operating Temperature Range

HI3-5700J-5, HI9P5700J-5 0°C to +75°C

HI3-5700A-9, HI9P5700A-9 -40°C to +85°C

Junction Temperature +150°C

Storage Temperature Range -65°C to +150°C

Lead Temperature (Soldering, 10 sec.) 300°C

NOTE:

Thermal Information

Thermal Resistance 8^ 8 |c

HI3-5700J-5, HI3-5700A-9 50°C/W 20°C/W

HI9P5700J-5, HI9P5700A-9 71°CAV 22°CAV

Power Dissipation at +75°C (Note 1)

HI3-5700J-5, HI3-5700A-9 1500mW

HI9P5700J-5, HI9P5700A-9 1100mW

Power Dissipation Derating Factor Above +75°C

HI3-5700J-5, HI3-5700A-5 20mW/°C

HI9P5700J-5, HI9P5700A-9 14mW/°C

1 . Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

CAUTION: Stresses above those listed in the 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and opera-
tion of the device at these or any other conditions above those indicated in the operation section ot this specification is not implied.

Electrical Specifications AV DD = V DD = +5.0V; V REFi = +4.0V; V HEF . = GND = AGND = 0V; F s = Specified Clock Frequency e
50% Duty Cycle; C L = 30pF; Unless Otherwise Specified.

PARAMETER

TEST CONDITION

+25°C

(NOTE 2)
0°C to +75°C
-40°C to +85"C

UNITS

MIN

TYP

MAX

MIN

MAX

ACCURACY

Resolution

Bits

Integral Linearity Error (INL)
(Best Fit Method)

F s = 15MHz, f, N = DC
F s = 20MHz, f, N = DC

±0.9
±1.0

±2.0
±2.25

±2.25
±3.25

LSB
LSB

Differential Linearity Error (DNL)
(Guaranteed No Missing Codes)

F s = 15MHz, f, N = DC
F s = 20MHz, f, N = DC

±0.4
±0.5

±0.9
±0.9

±1.0
±1.0

LSB
LSB

Offset Error (VOS)

F s = 15MHz, f, N = DC
F s = 20MHz, f, N = DC

±5.0
±5.0

±8.0
±8.0

±9.5
±9.5

LSB
LSB

Full Scale Error (FSE)

F s = 15MHz, f, N = DC
F s m 20MHz, f|N = DC

±0.5
±0.6

±4.5
±4.5

±8.0
±8.0

LSB
LSB

DYNAMIC CHARACTERISTICS

Maximum Conversion Rate

No Missing Codes

MSPS

Minimum Conversion Rate

No Missing Codes (Note 2)

0.125

MSPS

Full Power Input Bandwidth

F s = 20MHz

MHz

Signal to Noise Ratio (SNR)
RMS Signal

F s = 15MHz, f IN = 100kHz
F s = 15MHz, f, N = 3.58MHz
F s = 15MHz, f, N = 4.43MHz
F s = 20MHz, f, N = 100kHz
F s = 20MHz, f, N = 3.58MHz
F s = 20MHz, f, N = 4.43MHz

46.5
44.0
43.4
45.9
42.0
41.6

dB
dB
dB
dB
dB
dB

Signal to Noise Ratio (SINAD)
RMS Signal

RMS Noise + Distortion

F s = 15MHz, f, N = 100kHz
F s = 15MHz, f IN = 3.58MHz
F s = 15MHz, f, N = 4.43MHz
F s = 20MHz, f IN = 100kHz
F s = 20MHz, f, N = 3.58MHz
F s = 20MHz, f| N = 4.43MHz

43.4
34.3
32.3
42.3
35.2
32.8

dB
dB
dB
dB
dB
dB

1-53

Specifications HI-5700

Electrical Specifications AV DD = V DD = +5.0V; V REF , = +4.0V; V REF . = GND = AGND = OV; F s = Specified Clock Frequency @
50% Duly Cycle; C L = 30pF; Unless Otherwise Specified. (Continued)

+25°C

(NOTE 2)
0°C to +75°C
-40°C to +85°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

MIN

MAX

UNITS

Total Harmonic Distortion

F s = 15MHz, f, N = 100kHz
F s = 15MHz, f IN = 3.58MHz
F s = 15MHz. f, N = 4.43MHz
F s = 20MHz, f, N = 100kHz
F s = 20MHz, f IN = 3.58MHz
F s = 20MHz, f, N = 4.43MHz

-46.9
-34.8
-32.8
-46.6
-36.6
-33.5

dBc
dBc
dBc
dBc
dBc
dBc

Differential Gain

F s = 14MHz, f IN = 3.58MHz

3.5

Differential Phase Error

F s = 14MHz, f IN = 3.58MHz

0.9

Degree

ANALOG INPUT

Analog Input Resistance, R| N
Analog Input Capacitance, C IN
Analog Input Bias Current, IB

V, N = 4V
V| N = 0V
V IN = 0V, 4V

10
60
±0.01

±1.0

pF
uA

REFERENCE INPUT

Total Reference Resistance, R L

250

330

235

Reference Resistance Tempco, T c

+0.31

£5/°C

DIGITAL INPUTS

Input Logic High Voltage, V, H
Input Logic Low Voltage, V IL
Input Logic High Current, l IH
Input Logic Low Current, l| L
Input Capacitance, C| N

V IN = 5V
V IN = 0V

2.0

0.8
1.0
1.0

2.0

0.8
1.0
1.0

V
V
uA
UA
pF

DIGITAL OUTPUTS

Output Logic Sink Current, l OL
Output Logic Source Current, l 0H
Output Leakage, l z
Output Capacitance, Cqut

V = 0.4V
V = 4.5V

CE2 = 0V, V = 0V, 5V
CE2 = OV

3.2
-3.2

5.0

±1.0

3.2
-3.2

±1.0

mA
mA
uA
pF

TIMING CHARACTERISTICS

Aperture Delay, t AP
Aperture Jitter, t w
Data Output Enable Time,
Data Output Disable Time, t D | S
Data Output Delay, to D
Data Output Hold, t H

6
30
18
15
20
20

25
20
25

30
25
30

ns
ns
ns
ns

POWER SUPPLY REJECTION

Offset Error PSRR, AVOS
Gain Error PSRR, AFSE

V OD = 5V±10%
V DD = 5V±10%

±0.1
±0.1

±2.75
±2.75

±5.0
±5.0

LSB
LSB

POWER SUPPLY CURRENT

Supply Current, l DD

F s = 20MHz

145

180

190

NOTE:

2. Parameter guaranteed by design or characterization and not production tested.

1-54

HI-5700

Timing Waveforms

CLOCK

ENCODER DATA IS
COMPARATOR DATA LATCHED INTO THE

IS LATCHED OUTPUT REGISTERS

/ /
SAMPLE SAMPLE SAMPLE £_ SAMPLE 'SAMPLE ,

N-2 / AUTO \ N-1 / AUTO \ N / AUTO \ N+1 / AUTO \ N+2 /

FIGURE 1. INPUT-TO-OUTPUT TIMING

CE1

CE2

D0-D7

tois

H**1

DATA

y DATA S
*S /

OVF

DATA

IMPEDANCE

DATA

FIGURE 2. OUTPUT ENABLE TIMING

1-55

HI-5700

Typical Performance Curves

EFFECTIVE NUMBER OF BITS vs fin

EFFECTIVE NUMBER OF BITS vs TEMPERATURE

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT FREQUENCY - (In (MHz)

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140
TEMPERATURE (°C)

SNR vs TEMPERATURE TOTAL HARMONIC DISTORTION vs TEMPERATURE

TEMPERATURE (°C) TEMPERATURE (°C)

INL vs TEMPERATURE DNL vs TEMPERATURE

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140 -60 -40 -20 +20 +40 +60 +80 +100 +120 +140

TEMPERATURE (°C) TEMPERATURE (°C)

1-56

HI-5700

Typical Performance Curves (continued)

OFFSET VOLTAGE vs. TEMPERATURE

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140
TEMPERATURE (°C)

FULL SCALE ERROR vs TEMPERATURE

2 -i

■ 5V,

«4V

1.5-
1 -

0.5 -

F S -

20Mf

Fs-

15MK

+20 +40 +60 +80 +100 +120 +140
:(°C)

OUTPUT DELAY vs TEMPERATURE

= sv,'v R ef,

= 4V

AD =

OpF

toD

•ho

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140
TEMPERATURE (°C)

POWER SUPPLY REJECTION vs TEMPERATURE

VdO , = 5V,V bef J=4V

PSRR VOS

PSRR FSE

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140
TEMPERATURE (°C)

SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs CLOCK & DUTY CYCLE

-60 -40 -20 +20 +40 +60 +80 +100 +120 +140 0.1 1 10 1 00

TEMPERATURE (°C) CLOCK FREQUENCY (MHz)

1-57

HI-5700

TABLE 1. PIN DESCRIPTION

PIN #

NAME

DESCRIPTION

CLK

Clock Input

Bit 7, Output (MSB)

Bit 6, Output

Bit 5, Output

Bit 4, Output

1/4R

1/4th Point of Reference Ladder

V D D

Digital Power Supply

GND

Digital Ground

3/4R

3/4th Point of Reference Ladder

Bit 3, Output

Bit 2, Output

Bit 1, Output

Rit Oiitnnt il ^R^

OVF

CE2

ThroA 9tatp Oiitnnt Fnahlp Innut Art'ma Hinh
■ mot? oldie wuipui ciidum inpui, niftivo niyn.

(See Table 2)

CE1

Three State Output Enable Input, Active Low.
(See Table 2)

Vref*

Reference Voltage Positive Input

AVdd

Analog Power Supply, +5V

AGND

Analog Ground

AGND

Analog Ground

AV DD

Analog Power Supply, +5V

1/2R

1/2 Point of Reference Ladder

AV D d

Analog Power Supply, +5V

AGND

rti idiuy v_ji uui hj

AGND

Analog Ground

AVdd

Analog Power Supply, +5V

Vref-

Reference Voltage Negative Input

V IN

Analog Input

Theory of Operation

The HI-5700 is an 8 bit analog-to-digital converter based on
a parallel CMOS "flash'' architecture. This flash technique is
an extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 256 comparators
are used in the HI-5700: (2 s - 1) comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.

The CMOS HI-5700 works by alternately switching between
a "Sample" mode and an "Auto Balance" mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each con-
version cycle such that offset voltage drift is virtually elimi-
nated during operation. The block diagram and timing
diagram illustrate how the HI-5700 CMOS flash converter
operates.

The input clock which controls the operation of the HI-5700
is first split into a non-inverting <t>1 clock and an inverting <p2
clock. These two clocks, in turn, synchronize all internal tim-
ing of analog switches and control logic within the converter

In the "Auto Balance" mode ($1), all $1 switches close and
*2 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between GND and V DD and presenting a low
impedance to a small input capacitor. Each capacitor, in turn,
is connected to a reference voltage tap from the resistor
ladder. The Auto Balance mode quickly precharges all 256
input capacitors between the self-bias voltage and each
respective tap voltage.

In the "Sample" mode (4>2), all $1 switches open and <p2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The <j>2 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage differ-
ence between the reference tap and input voltage to the

comparator input. All 256 comparators are thus driven simul-
taneously to a defined logic state. For example, if the input
voltage is at mid-scale, capacitors precharged near zero dur-
ing $1 will push comparator inputs higher than the self bias
voltage at d>2; capacitors precharged near the reference volt-
age push the respective comparator inputs lower than the
bias point. In general, all capacitors precharged by taps
above the input voltage force a "low" voltage at comparator
inputs; those precharged below the input voltage force "high"
inputs at the comparators.

During the next $1 Auto- Balancing state, comparator output
data is latched into the encoder logic block and the first
stage of encoding takes place. The following $2 state com-
pletes the encoding process. The 8 data bits (plus overflow
bit) are latched into the output flip-flops at the next falling
clock edge. The Overflow bit is set if the input voltage
exceeds V REF+ - 0.5LSB. The output bus may be either
enabled or disabled according to the state of CE1 and CE2
(See Table 2). When disabled, output bits assume a high
impedance state.

As shown in the timing diagram, the digital output word
becomes valid after the second $1 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. "Data Output Delay" time indicates the slight
time delay for data to become valid at the end of the $1
state.

1-58

HI-5700

Applications Information

Voltage Reference

The reference voltage is applied across the resistor ladder
between V REF+ and V REF .. In most applications, V REF . is
simply tied to analog ground such that the reference source
drives V REF+ . The reference must be capable of supplying
enough current to drive the minimum ladder resistance of
235Q over temperature.

The HI-5700 is specified for a reference voltage of 4.0 volts,
but will operate with voltages as high as the V 0D supply. In
the case of 4.0 volt reference operation, the converter
encodes the analog input into a binary output in LSB incre-
ments of (V REF+ - V REF _)/256, or 1 5.6mV. Reducing the ref-
erence voltage reduces the LSB size proportionately and
thus increases linearity errors. The minimum practical refer-
ence voltage is about 2.5 volts. Because the reference volt-
age terminals are subjected to internal transient currents
during conversion, it is important to drive the reference pins
from a low impedance source and to decouple thoroughly.
Again, ceramic and tantalum (0.01 u,F and 10u,F) capacitors
near the package pin are recommended. It is not necessary
to decouple the 1/4R, 1/2R, and 3/4R tap point pins for most
applications.

It is possible to elevate V REF . from ground if necessary. In
this case, the V REF . pin must be driven from a low imped-
ance reference capable of sinking the current through the
resistor ladder. Careful decoupling is again recommended.

Digital Control and Interface

The HI-5700 provides a standard high speed interface to
external CMOS and TTL logic families. Two chip enable
inputs control the three-state outputs of output bits DO
through D7 and the Overflow (OVF) bit. As indicated in the
Truth Table, all output bits are high impedance when CE2 is
low, and outpu t bits DO through D7 are independently con-
trolled by CE1.

Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge cur-
rents will produce supply and local group disturbances.
Therefore, an external bus driver is recommended.

Clock

The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the conver-
sion frequency and controls the converter as described in
the "Theory of Operation" section. The Auto Balance <|>1 half
cycle of the clock may be reduced to approximately 20ns;
the Sample <f>2 half cycle may be varied from a minimum of
25ns to a maximum of 5us.

Signal Source

A current pulse is present at the analog input (V, N ) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch

feedthrough in the capacitor array. It varies with the ampli-
tude of the analog input and the converter's sampling rate.

The signal source must absorb these transients prior to the
end of the sample period to ensure a valid signal for conver-
sion. Suitable broad band amplifiers or buffers which exhibit
low output impedance and high output drive include the
HFA-0005, HA-5004, HA-5002, and HA-5003.

The signal source may drive above or below the power sup-
ply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +0.5LSB are
converted to all zeroes; input voltages of V REF+ -0.5LSB to
V DD +0.5V are converted to all ones with the Overflow bit
set.

Full Scale Offset Error Adjustment

In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and refer-
ence tap point trims. In general, offset and gain correction
can be done in the preamp circuitry.

Offset Adjustment

Offset correction can be done in the preamp driving the con-
verter by introducing a DC component to the input signal. An
alternate method is to adjust V REF - to produce the desired
offset. It is adjusted such that the to 1 code transition
occurs at 0.5LSB.

Gain Adjustment

In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V REF + voltage. The refer-
ence voltage is the ideal location.

Quarter Point Adjustment

The reference tap points are brought out for linearity adjust-
ment or creating a nonlinear transfer function if desired. It is
not necessary to decouple the 1/4R, 1/2R, and 3/4R tap
points in most applications.

Power Supplies

The HI-5700 operates nominally from 5 volt supplies but will
work from 3 volts to 6 volts. Power to the device is split such
that analog and digital circuits within the HI-5700 are pow-
ered separately. The analog supply should be well regulated
and "clean" from significant noise, especially high frequency
noise. The digital supply should match the analog supply
within about 0.5 volts and should be referenced externally to
the analog supply at a single point. Analog and digital
grounds should not be separated by more that 0.5 volts. It is
recommended that power supply decoupling capacitors be
placed as close to the supply pins as possible. A combina-
tion of 0.01 u.F ceramic and 10uF tantalum capacitors is rec-
ommended for this purpose as shown in the test circuit.

1-59

HI-5700

Reducing Power Consumption TABLE 2 - CHIP enable truth table

Power dissipation in the HI-5700 is related to clock
frequency and clock duty cycle. For a fixed 50% clock duty
cycle, power may be reduced by lowering the clock
frequency. For a given conversion frequency, power may be
reduced by decreasing the Auto-Balance (<|>1) portion of the
clock duty cycle. This relationship is illustrated in the
performance curves.

X's = Don't Care.

TABLE 3. CODE TABLE

CODE

INPUT VOLTAGE*
V BE F.= 4.0V
V REF . = 0.0V
(V)

DECIMAL

MSB

BINARY OUTPUT CODE

LSB

DESCRIPTION

COUNT

OVF

Overflow (OVF)

4.000

511

Full Scale (FS)

3.9375

255

]

FS - 1 LSB

3.875

254

3/4 FS

3.000

192

1/2 FS

2.000

128

1/4 FS

1.000

1 LSB

0.0156

Zero

• The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.

ceT

CE2

DO - D7

OVF

Valid

Three-State

Valid

Three-State

1-60

HI-5700

TO ANALOG GND

FIGURE 3. TEST CIRCUIT

Glossary of Terms

Aperture Delay: Aperture delay is the time delay between
the external sample command (the rising edge of the clock)
and the time at which the signal is actually sampled. This
delay is due to internal clock path propagation delays.

Aperture Jitter: This is the RMS variation in the aperture
delay due to variation of internal <|>1 and <)>2 clock path delays
and variation between the individual comparator switching
times.

Differential Linearity Error (DNL): The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of each
midpoint is 1.0LSB. The range of values possible is from
-1.0LSB (which implies a missing code) to greater than
+1.0LSB.

Full Power Input Bandwidth: Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude
of an input sine wave. The input sine wave has a peak-to-
peak amplitude equal to the reference voltage. The band-
width given is measured at the specified sampling frequency.

Full Scale Error (FSE): Full Scale Error is the difference
between the actual input voltage of the 254 to 255 code tran-
sition and the ideal value of V REF+ - 1.5LSB. This error is
©x|Dr@ss@d in L^L^s.

Integral Linearity Error (INL): The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are cal-
culated using a best fit line through the converter's transfer
function.

LSB: Least Significant Bit = (V REF+ - V REF _)/256. All HI-5700
specifications are given for a 1 5.6mV LSB size V REF+ = 4.0V,
V REF . = 0.0V.

Offset Error (VOS): Offset error is the difference between
the actual input voltage of the to 1 code transition and the
ideal value of V REF . + 0.5LSB, V os Error is expressed in
LSBs.

Power Supply Rejection Ratio (PSRR): PSRR is
expressed in LSBs and is the maximum shift in code transi-
tion points due to a power supply voltage shift. This is mea-
sured at the to 1 code transition point and the 254 to 255
code transition point with a power supply voltage shift from
the nominal value of 5.0V.

Signal to Noise Ratio (SNR): SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.

Signal to Noise and Distortion Ratio (SINAD): SINAD is
the ratio in dB of the RMS signal to the RMS sum of the
noise and harmonic distortion at specified input and sam-
pling frequencies.

Total Harmonic Distortion (THD): THD is the ratio in dBc of
the RMS sum of the first five harmonic components to the
RMS signal for a specified input and sampling frequency.

1-61

SEMICONDUCTOR

HI-5700/883

July 1992

8-Bit, 20MSPS Flash A/D Converter

Features

• This Circuit is Processed in Accordance to Mll-Std-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• 20MSPS with No Missing Codes

• 18MHz Full Power Input Bandwidth

• No Missing Codes Over Temperature

• Sample and Hold Not Required

• Single +5V Supply Voltage

• CMOS/TTL

• Overflow Bit

Applications

• Video Digitizing

• Radar Systems

• Medical Imaging

• Communication Systems

• High Speed Data Acquisition Systems

Description

The HI-5700/883 is a monolithic, 8-bit, CMOS Flash Analog-
to-Digital Converter. It is designed for high speed applica-
tions where wide bandwidth and low power consumption are
essential. Its 20MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5700/883 delivers ±0.5LSB
differential nonlinearity while consuming only 725mW (typi-
cal) at 20MSPS. Microprocessor compatible data output
latches are provided which present valid data to the output
bus 1.5 clock cycles after the convert command is received.
An overflow bit is provided to allow the series connection of
two converters to achieve 9 bit resolution.

Ordering Information

PART NUMBER

TEMPERATURE
RANGE

PACKAGE

HI1-5700S/883

-55°Cto+125°C

28 Pin CERDIP

Pinout

28 PIN CERCIP

TOP VIEW

clk|T

2|V IN

D7[T

27]V nEF .

DS|T

§AV DD

D5(T

2§ AGND

D4[£

24] AGND

1/4R[T

Hav dd

Vdo|T

22|1/2R

gnd[T

2l]AV DD

3/4R[g

20j AGND

D3Qo

ISjAGND

D2QT

1|AV D[)

D1 Q2

gv BEF .

DOlTj

gcET

OVFfu

l|CE2

Functional Block Diagram

VREF^OZr

3/4R[T|-

iraRgU-

i H' l^COMP

1/4R[£)-

VflEF-HZr

R/2

r4h

f 183

CO,

I 8

-s-

-^-[S]D4

CLK [Tj [

-^-[2] D7 (MSB)
S D6

D3
D2
D1

01
- 02

4Q---j-01«.(LSB)
— JJJ|CE2

Voo[T| AV DD |3]f|l]^]0
gno [J] »ono|4]||]|19]|3

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright ©Harris Corporation 1992

File Number 3286

HI-5700/883

Pin Descriptions

PIN*

NAME

PIN*

NAME

DESCRIPTION

CLK

f'Mn/'t Innitt
V_>IUOK llipul

MV D0

Analog Power Supply, +5V

Rit 7 C)i itni it fMQR\

AGND

Analog Ground

Rit fi r% itni it
Dll O, VJUtpul

AGND

Analog Ground

Rit C /"li itni it
Dll 0, UUipUl

AM
A»DD

Analog Power Supply, +5V

nit a r"v itnut
D(I 4, UUtpUt

1/2R

1/2 Point ot Reference Ladder

1/4R

t lAth Dnint nf Dafaunoa 1 nHnar

i/4in roini oi neierenc© Laaaer

AV DD

Analog Power Supply, +5V

Vdd

Dinitai Pnuiar ^nnnlu
LMyiUSI "UWbl ouppiy

AGND

Analog Ground

GND

AGND

Analog Ground

3/4R

QMtti Dnint nl Dolaranao 1 nririnr

o/*»m r oini oi neierence Laaaer

avdd

Analog Power Supply, +5V

Rit 1 O* itni it

dii o, vjuipui

V BEF-

Reference Voltage Negative Input

Rit 9 Oi itni it
Dll £., *-^uipui

V,N

Analog Input

Rit 1 Oi itni it
Dll 1 , LAJlOUl

Bit 0, Output (USB)

Chip Enable Truth Table

OVF

Overflow, Output

CE1

CE2

D0-D7

OVF

CE2

1 ill tit; oldie LJUtpUl CNdUle llipui,

Active High. (See Truth Table)

Valid

Three-State

Valid

CE1

Three State Output Enable Input,
Active Low. (See Truth Table))

Three- State

Three-State

Vref*

Reference Voltage Positive Input

X = Don't Care.

1-63

Specifications HI-5700/883

Absolute Maximum Ratings

Supply Voltage, V DD to GND (GND - 0.5) < V DD < +7.0V

Analog and Reference Input Pins. . (Vgg - 0.5) < V, NA < (V D0 +0.5V)

Digital I/O Pins (GND - 0.5) <V IX) < (V DD +0.5V)

Operating Temperature Range

HI1-5700S/883 -55°C to +125°C

Junction Temperature +175°C

Storage Temperature Range -65°C to +1 50°C

Lead Temperature (Soldering, 10 sec.) 300°C

ESD Clasification Class 1

28°C/W

Thermal Information

Thermal Resistance Oj,
HI1-5700S/883 47°C/W

Power Dissipation at +75°C (Note 1)
HI1-5700S/883 2100mW

Power Dissipation Derating Factor Above +75°C
HI1-5700S/883 21mW/°C

Reliabiliy Infonnation

Transistor Count 14677

Worst Case Density 3.05 x itfA/cm 2

NOTE:

1 . Dissipation rating assumes device is mounted with all leads
soldered to printed circuit board.

CAUTION: Stresses above those listed in 'Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: AV DD = V DD = +5.0V; V REF , = +4.0V; V REF . = GND = AGND = 0V; F s = Specified Clock Frequency © 50% Duty Cycle;
C L = 30pF; Unless Otherwise Specified.

DC PARAMETERS

SYMBOL

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNIT

MIN

MAX

ACCURACY

Integral Linearity Error
(Best Fit Method)

INL

F s = 15MHz, f in = DC

+25°C

±2.0

LSB

2,3

+125°C, -55°C

±2.65

LSB

F s = 20MHz, f in = DC

+25°C

±2.25

LSB

2,3

+125°C, -55°C

±4.1

LSB

Differential Linearity Error
(Guaranteed No Missing
Codes)

DNL

F s =15MHz,f in = DC

+25°C

±0.9

LSB

2,3

+125°C, -55°C

±1.0

LSB

F s = 20MHz, f in = DC

+25°C

±0.9

LSB

2,3

+125°C, -55°C

±1.0

LSB

Offset Error
(Adjustable to zero)

VOS

F s = 15MHz, f in = DC

+25°C

±8.0

LSB

2,3

+125°C, -55°C

±9.5

LSB

F s = 20MHz, f>„ = DC

+25°C

±8.0

LSB

2,3

+125°C, -55°C

±9.5

LSB

Full Scale Error
(Adjustable to zero)

FSE

F s = 15MHz, f in = DC

+25°C

±4.5

LSB

2,3

+125°C, -55°C

±8.0

LSB

F s = 20MHz, f in = DC

+25°C

±4.5

LSB

2,3

+125°C, -55°C

±8.0

LSB

ANALOG INPUT

Analog Input Resistance

R IN

V IN = 4V

+25°C

M£2

2,3

+125°C, -55°C

Analog Input Bias Current

V IN = 0V,4V

+25°C

±1.0

2,3

+125°C, -55°C

±1.0

1-64

Specifications HI-5700/883

TABLE 1 . DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Tested at: AV DD = V DD = +5.0V; V REF , = +4.0V; V HEF . = GND = AGND = OV; F s = Specified Clock Frequency ® 50% Duty Cycle;
C L = 30pF; Unless Otherwise Specified.

DC PARAMETERS

SYMBOL

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNIT

MIN

MAX

REFERENCE INPUT

Total Reference Resistance

+25°C

250

2,3

+125°C, -55°C

235

DIGITAL INPUTS

Input High Voltage

V,H

+25°C

2.0

2,3

+125°C, -55°C

2.0

Input Low Voltage

V,L

+25°C

0.8

2,3

+125°C, -55°C

0.8

Logic Input Current

■in

V, N = 0V, +5V

+25°C

±1

2,3

+125°C, -55°C

±1

DIGITAL OUTPUTS

Output Leakage

taz

CE2 = 0V,V o = 0V,5V

+25°C

±1.0

2,3

+125°C, -55°C

±1.0

Output Logic Source Current

'oh

V = 4.5V

+25°C

-3.2

2,3

+125°C, -55°C

-3.2

Output Logic Sink Current

l0L

V = 0.4V

+25°C

3.2

2,3

+125°C, -55°C

3.2

POWER SUPPLY REJECTION

Offset Error PSRR

AVOS

V DD = 5V±10%

+25°C

±2.75

LSB

2,3

+125°C, -55°C

±5.5

LSB

Gain Error PSRR

AFSE

V DO = 5V±10%

+25°C

±2.75

LSB

2,3

+125°C, -55°C

±5.5

LSB

POWER SUPPLY CURRENT

Supply Current

F s = 20MHz

+25°C

180

2,3

+125°C, -55°C

190

1-65

Specifications HI-5700/883

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: AV DD = V DD = +5.0V; V REF< . = 44.0V; V REF . = GND = AGND = 0V; F s = Specified Clock Frequency © 50% Duty Cycle;
C L = 30pF; Unless Otherwise Specified.

AC PARAMETER

SYMBOL

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNIT

MIN

MAX

Maximum Conversion Rate

No Missing Codes

+25°C

MSPS

10,11

+125°C, -55°C

MSPS

Data Output Enable Time

+25°C

10, 11

+125°C, -55°C

Data Output Disable Time

tois

+25°C

10, 11

+125°C, -55°C

Data Output Delay

toD

+25°C

10, 11

+125°C, -55°C

Data Output Hold

1+1

+25°C

10, 11

+125°C, -55°C

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Characterized at: AV DD = V D0 = +5.0V; V REF ^ = +4.0V; V REF . = GND = AGND = 0V; F s = Specified Clock Frequency © 50% Duty
Cycle; C L = 30pF; Unless Otherwise Specified.

PARAMETER

SYMBOL

CONDITIONS

TEMPERAUTRE

LIMITS

UNIT

MIN

MAX

Minimum Conversion Rate

No missing codes

+25°C, +125°C,-55°C

0.125

MSPS

NOTE:

2. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These pa-
rameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by character-
ization based upon data from multiple production runs which reflect lot to lot and within lot variation.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

MIL-STD-883 TEST REQUIREMENTS

SUBGROUPS (SEE TABLES 1 & 2)

Interim Electrical Parameters (Pre Burn-In)

Final Electrical Test Parameters

1*, 2, 3, 9, 10, 11

Group A Test Requirements

1,2, 3, 9,10,11

Groups C & D Endpoints

• PDA applies to Subgroup 1 only. No other subgroups are included in PDA.

1-66

Specifications HI-5700/883

Timing Waveforms

C ,NpSt / AUTO \ ""N-l" / AUTO \~ * I AUTO \ / AUTO \ "N+2 /

SAMPLE

ENCODER DATA IS
LATCHED INTO THE
OUTPUT F

SAMPLE

OUTPUT DATA N-4 ^ DATA N-3 ) >< ^ DATA N-2 ^ DATA N-1 ^ X ^~ DATA j

FIGURE 1. INPUT-TO-OUTPUT TIMING

CE1

\ V

'cms

-I I

°°- m ~^r\ HIGH / DATA N HIGH / DATA
/ IMPEDANCEN / IMPEDANCE\

OVF

DATA

\ HIGH /
/ IMPEDANCE\

DATA

FIGURE 2. OUTPUT ENABLE TIMING

1-67

HI-5700/883

Burn-In Circuit

HI-5700/883 CERAMIC DIP

10 DUTY CYCLE

1 00kHz; < V< 5 VOLTS

CE2 15}

O +5.SV

GND

0.01|lF

TRIANGLE-WAVEFORM;
'in a

jfcO.OIpiF il^F

VGNO

V GND

1-68

HI-5700/883

Metallization Topology

DIE DIMENSIONS:

154.3 x 173.2 x19±1mils

METALLIZATION:

Type: Si-AI
Thickness: 11kA±1kA

GLASSIVATION:

Type: SiO z

Thickness: 8kA ± 1kA

DIE ATTACH:

Material: Gold Silicon Eutectic Alloy
Temperature:Ceramic DIP - 460°C (Max)

WORST CASE CURRENT DENSITY:

3.05 x 10 4 A/cm 2

Metallization Mask Layout

1-69

HI-5700/883

Packaging*

28 PIN CERAMIC DIP

.150
.180

.150 WIN

098 MAX

.535

.595

— ^ .008 *"
.015

IS*

INCREASE MAX LIMIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
• SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A

PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:

Material: Glass Frit
Temperature: 450°C ± 10°C
Furnace Seal

INTERNAL LEAD WIRE:

Material: Aluminum
Diameter: 1.25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510-D-10

NOTE: All Dimensions are "j". Dimensions are in inches.

t Mil-M-38510 Compliant Materials, Finishes and Dimensions

1-70

m HARRIS

SEMICONDUCTOR

HI-5701

July 1992

6 Bit, 30 MSPS Flash A/D Converter

Features

• 30 MSPS with No Missing Codes

• 20MHz Full Power Input Bandwidth

• No Missing Codes Over Temperature

• Sample and Hold Not Required

• Single +5V Supply Voltage

• 300mW (Max) Power Dissipation

• CMOS/TTL Compatible

• Overflow Bit

Applications

• Video Digitizing

• Radar Systems

• Communication Systems

• High Speed Data Acquisition Systems

Description

The HI-5701 is a monolithic, 6 bit, CMOS flash Analog-to-
Digital Converter. It is designed for high speed applications
where wide bandwidth and low power consumption are
essential. Its 30 MSPS speed is made possible by a parallel
architecture which also eliminates the need for an external
sample and hold circuit. The HI-5701 delivers ±0.7LSB
differential nonlinearity while consuming only 250mW
(typical) at 30 MSPS. Microprocessor compatible data
output latches are provided which present valid data to the
output bus 1.5 clock cycles after the convert command is
received. An overflow bit is provided to allow the series
connection of two converters to achieve 7 bit resolution.

The HI-5701 is available in Commercial and Industrial
temperature ranges and is supplied in 18 pin Plastic DIP and
SOIC packages.

Ordering Information

PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

HI3-5701K-5

0°C to +75°C

18 Pin Plastic DIP

HI9P5701K-5

0°C to +75°C

18 Pin SOIC

HI3-5701B-9

-40°C to +85°C

18 Pin Plastic DIP

HI9P5701B-9

-40°C to +85°C

18 Pin SOIC

Pinout

18 PIN PLASTIC DIP AND SOIC
TOP VIEW

OS (MSB) [7

18] D4

OVF [I

17] D3

Vss [I

)5] 1«R

NC [7

ij] 02

CE2 [?

U] D1

ceT [T

13] DO (LSB)

CLK [T

•HVdo

PHASE |T

n]v w

VflEF, LI

LIDvref.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1992

File Number 2937.3

HI-5701

Functional Block Diagram

01 02 01 01 02

1-72

Specifications HI-5701

Thermal Information

75°C/W
95°C/W

6 ic
26°C/W

26°C/W

Absolute Maximum Ratings

Supply Voltage, V D0 to V ss (Vss - 0.5) < V 0D < +7.0V

Analog and Reference Input Pins (Vss " 0.5) < V,^ <: (V DD -(0.5V)

Digital I/O Pins (V^ - 0.5) < V,yo < (V DD +0-5V)

Operating Temperature Range

HI3-5701-5 0°Cto+75°C

HI9P5701-9 -40°C to +65°C

Junction Temperature +1 50°C

Storage Temperature Range -65°C to +150°C

Lead Temperature (Soldering, 10 sec.) 300°C

NOTE:

1 . Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

Thermal I

HI3-5701

HI9P5701

Power Dissipation at +75°C (Note 1)

HI3-5701-5 1000mW

HI9P5701-9 790mW

Power Dissipation Derating Factor Above +75°C

HI3-5701-5 13mW/°C

HI9P5701-9 10.5mW/°C

Electrical Specifications: V DD = +5.0V; V REF , = +4.0V; V REF . = V^ = GND; F s = Specified Clock Frequency © 50% Duty Cycle;
C L - 30pF; Unless Otherwise Specified.

PARAMETER

TEST CONDITION

+25°C

(NOTE 2)
0°C to +75°C
-40°C to +85°C

UNITS

MIN

TYP

MAX

MIN

MAX

SYSTEM PERFORMANCE

Resolution

Bits

Integral Linearity Error (INL)
(Best Fit Line)

F s = 20MHz
F s = 30MHz

±0.5
±1.5

±1.25

±2.0

LSB
LSB

Differential Linearity Error (DNL)
(Guaranteed No Missing Codes)

F s > 20MHz
F s = 30MHz

±0.3
±0.7

±0.6

±0.75

LSB
LSB

Offset Error (VOS)
(Adjustable to Zero)

F s = 20MHz (Note 2)
F s = 30MHz

±0.5
±0.5

±2.0

±2.5

LSB
LSB

Full Scale Error (FSE)
(Adjustable to Zero)

F s = 20MHz (Note 2)
F s = 30MHz

±0.25
±0.25

±2.0

±2.5

LSB
LSB

DYNAMIC CHARACTERISTICS

Maximum Conversion Rate

No Missing Codes

MSPS

Minimum Conversion Rate

No Missing Codes (Note 2)

0.125

MSPS

Full Power Input Bandwidth

F s = 30MHz

MHz

Signal to Noise Ratio (SNR)
RMS Signal

RMS Nois©

F s = 1 MHz, f, N = 100kHz
F s = 30MHz, f m = 4MHz

36
31

dB
dB

Signal to Noise Ratio (SINAD)
RMS Signal

RMS Noise + Distortion

F s = 1 MHz, f, N = 100kHz
F s = 30MHz, f iN = 4MHz

35
30

dB
dB

Total Harmonic Distortion

F s = 1 MHz, f, N = 100kHz
F s = 30MHz, f, N = 4MHz

-44

-38

dBc
dBc

Differential Gain

F s = 14.32MHz, f lN = 3.58MHz

Differential Phase

F s = 14.32MHz, f IN = 3.58MHz

Degree

ANALOG INPUT

1-73

Specifications HI-5701

Electrical Specifications: V DD = +5.0V; V REF „ = +4.0V; V REF . = Vss = GND; F 3 = Specified Clock Frequency © 50% Duty Cycle;
C L = 30pF; Unless Otherwise Specified. (Continued)

PARAMETER

+25°C

(NOTE 2)
e Cto+75°C
-40°C to +85°C

UNITS

MIN

TYP

MAX

MIN

MAX

Analog Input Resistance, R m
Analog Input Capacitance, C IN
Analog Input Bias Current, IB

V, N = 4V

v, N = ov

V lN = 0V,4V

30
20
0.01

±1.0

pF
UA

REFERENCE INPUT

Total Reference Resistance, R L

250

370

235

Reference Resistance Tempco, T^

+0.266

arc

DIGITAL INPUTS

Input Logic High Voltage, V IH
Input Logic Low Voltage, V, L
Input Logic High Current, l IH
Input Logic Low Current, l| L
Input Capacitance, C IN

Vim = 5V
V, N = 0V

2.0

0.8
1.0
1.0

2.0

0.8
1.0
1.0

V
V
MA
|iA
PF

DIGITAL OUTPUTS

Output Logic Sink Current, l i_
Output Logic Source Current I h
Output Leakage, I ff
Output Capacitance, Cqut

V = 0.4V
V = 4.5V
CE2 = 0V
CE2 = 0V

3.2
-3.2

5.0

±1.0

3.2
-3.2

±1.0

mA
mA
uA
PF

TIMING CHARACTERISTICS

Aperture Delay, t AP
Aperture Jitter, t w
Data Output Enable Time, t^
Data Output Disable Time, tois
Data Output Delay, too
Data Output Hold, t^

(Note 2)
(Note 2)
(Note 2)
(Note 2)

6
30
12
11
14
10

20
20
20

ns
ns
ns
ns

POWER SUPPLY REJECTION

Offset Error PSRR, AVOS
Gain Error PSRR, AFSE

V DD = 5V±10%
V DD = 5V± 10%

±0.1
±0.1

±1.0
±1.0

±1.5
±1.5

LSB
LSB

POWER SUPPLY CURRENT

Supply Current, l DD

F s = 30MHz

75 mA

NOTE:

2. Parameter guaranteed by design or characterization and not production tested.

1-74

HI-S701

Timing Waveforms

CLOCK

HIGH 02

i 01 r^r\ 01 f

IS LATCHED

CLOCK

SAMPLE SAMPLE

AUTi
MM

SAMPLE

ENCODED DATA IS
LATCHED INTO THE
OUTPUT REGISTERS

N ' 2 / AUTO \ N ' 1 / AUTO \ N / AUTO \ w + 1 / AUTO
LOW BALANCE i. BALANCE i BALANCE BALANCE

ANALOG
INPUT

DATA
OUTPUT

SAMPLE

n+2 r

DATA N-4 ^>^~

DATA N-3

DATA N-2

^X ^ DATA N-1 ^ DATAN

FIGURE 1. INPUT-TO-OUTPUT TIMING

1 /

ins

•en

•cms

D0-D5

OVF

"T~IT \ HIGH / ~~~~ \ HIGH / ~~~

DATA > ( DATA > — ( DATA

/IMPEDANCE\ / IMPEDANCE\

DATA

'EN

FIGURE 2. OUTPUT ENABLE TIMING

1-75

HI-5701

Typical Performance Curves

EFFECTIVE NUMBER OF BITS VS f IN

1
m

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT FREQUENCY (l M ) - MHz

ENOB V* TEMPERATURE

F s -1

MHz,l*.

100kHz

S = 3

DMH

*4M

DO =

= 4V

-40 -30 -20 -10 10 20 30 40 50 SO 70
TEMPERATURE (°C)

INL VS TEMPERATURE

DNL VS TEMPERATURE

m 1

'IN

= 1C
B-l

OkH

V, V

IE Ft

= 4V

■ 30

■ 1|

m 05

-40 -30 -20 -10 10 20 30 40 50 60 70 80
TEMPERATURE (°C)

"1<
O-

KJkH

>V, V

REF+

= 4\

S = 3

0MH

S =

-40 -30 -20 -10 10 20 30 40 50 60 70 80
TEMPERATURE <°C)

1-76

HI-5701

Typical Performance Curves (Continued)

POWER SUPPLY REJECTION vt TEMPERATURE

— 1
Vk

= 5\

1 ±

10%

Vre

I — I

—

PSR

RV<

(

SRR

FSE

-10 10 20 30 40 50
TEMPERATURE (°C)

60 70 SO SO

SUPPLY CURRENT vs TEMPERATURE

20 40 60

TEMPERATURE (°C)

100

SUPPLY CURRENT vs CLOCK AND DUTY CYCLE

1 10
CLOCK FREQUENCY (MHz)

100

1-77

HI-5701

TABLE 1. PIN DESCRIPTION

PIN#

NAME

DESCRIPTION

Bit 6, Output (MSB)

OVF

Overflow, Output

Vss

Digital Ground

No Connection

CE2

Three-State Output Enable Input, Active
High (See Table 2).

ClT

Three-State Output Enable Input, Active
Low (See Table 2).

CLK

Clock Input

PHASE

Sample Clock Phase Control Input.
When Phase is Low, Sample Unknown
(01 ) Occurs When the Clock Is Low and
Auto Balance (02) Occurs When the
Clock is High (See Text).

Reference Voltage Positive Input

v BEF .

Reference Voltage Negative Input

V IN

Analog Signal Input

Vdd

Power Supply, +5V

Bit 1, Output (LSB)

Bit 2, Output

Bit 3, Output

1/2 R2

Reference Ladder Midpoint

Bit 4, Output

Bit 5, Output

Theory of Operation

The HI-5701 Is a 6 bit analog-to-digital converter based on a
parallel CMOS "flash" architecture. This flash technique is an
extremely fast method of A/D conversion because all bit
decisions are made simultaneously. In all, 64 comparators
are used in the HI-5701; 63 comparators to encode the
output word, plus an additional comparator to detect an
overflow condition.

The CMOS HI-5701 works by alternately switching between
a "Sample" mode and an "Auto Balance" mode. Splitting up
the comparison process in this CMOS technique offers a
number of significant advantages. The offset voltage of each
CMOS comparator is dynamically canceled with each
conversion cycle such that offset voltage drift is virtually
eliminated during operation. The block diagram and timing
diagram illustrate how the HI-5701 CMOS flash converter
operates.

The input clock which controls the operation of the HI-5701
is first split into a non-inverting $1 clock and an inverting <p2
clock. These two clocks, in turn, synchronize all internal
timing of analog switches and control logic within the
converter.

In the "Auto Balance" mode (<|>1), all 4>1 switches close and
02 switches open. The output of each comparator is
momentarily tied to its own input, self-biasing the comparator
midway between V ss and V DD and presenting a low
impedance to a small input capacitor. Each capacitor, in
turn, is connected to a reference voltage tap from the
resistor ladder. The Auto Balance mode quickly precharges
all 64 input capacitors between the self-bias voltage and
each respective tap voltage.

In the "Sample" mode ($2), all $1 switches open and <t>2
switches close. This places each comparator in a sensitive
high gain amplifier configuration. In this open loop state, the
input impedance is very high and any small voltage shift at
the input will drive the output either high or low. The 02 state
also switches each input capacitor from its reference tap to
the input signal. This instantly transfers any voltage
difference between the reference tap and input voltage to the
comparator input. All 64 comparators are thus driven
simultaneously to a defined logic state. For example, if the
input voltage is at mid-scale, capacitors precharged near
zero during 01 will push comparator inputs higher than the
self bias voltage at 02; capacitors precharged near the
reference voltage push the respective comparator inputs
lower than the bias point. In general, all capacitors
precharged by taps above the input voltage force a "low"
voltage at comparator inputs; those precharged below the
input voltage force "high" inputs at the comparators.

During the next 01 state, comparator output data is
latched into the encoder logic block and the first stage of
encoding takes place. The following 02 state completes
the encoding process. The 6 data bits (plus overflow bit)
are latched into the output flip-flops at the next falling
clock edge. The Overflow bit is set if the input voltage
exceeds V REF+ - 1/2LSB. The output bus may be e ither
enabled or disabled according to the state of CE1 and
CE2 (See Table 2). When disabled, output bits assume a
high impedance state.

As shown in the timing diagram, the digital output word
becomes valid after the second 01 state. There is thus a one
and a half cycle pipeline delay between input sample and
digital output. "Data Output Delay" time indicates the slight
time delay for data to become valid at the end of the 01 state.
Refer to the Glossary of Terms for other definitions.

Applications Information

Voltage Reference

The reference voltage is applied across the resistor ladder at
the input of the converter, between V REFt and V REF .. In most
applications, V REF . is simply tied to analog ground such that
the reference source drives V REF+ . The reference must be
capable of supplying enough current to drive the minimum
ladder resistance of 235 Ohms over temperature.

1-78

HI-5701

The HI-5701 is specified (or a reference voltage of 4.0 volts,
but will operate with voltages as high as the V DD supply. In
the case of 4.0 volt reference operation, the converter
encodes the analog input into a binary output in LSB
increments of (V REF+ - V REF .)/64, or 62.5mV. Reducing the
reference voltage reduces the LSB size proportionately and
thus increases linearity errors. The minimum practical
reference voltage is about 2 volts. Because the reference
voltage terminals are subjected to internal transient currents
during conversion, it is important to drive the reference pins
from a low impedance source and to decouple thoroughly.
Again, ceramic and tantalum (O.OluF and 10u.F) capacitors
near the package pin are recommended. It is not necessary
to decouple the 1/2R tap point pin for most applications.

It is possible to elevate V REF . from ground if necessary. In
this case, the V REF . pin must be driven from a low
impedance reference capable of sinking the current through
the resistor ladder. Careful decoupling is again
recommended.

Digital Control and Interface

The HI-5701 provides a standard high speed interface to
external CMOS and TTL logic families. Four digital inputs
are provided to control the function of the converter. The
clock and phase inputs control the sample and auto balance
modes. The digital outputs change state on the clock phase
which begins the sample mode. Two chip enable inputs
control the three-state outputs of output bits DO through D5
and the Overflow OVF bit. As indicated in Table 2, all output
bits are high impedance when CE2 is low, a nd ou tput bits DO
through D5 are independently controlled by CE1 .

Although the Digital Outputs are capable of handling typical
data bus loading, the bus capacitance charge/discharge
currents will produce supply and local ground disturbances.
Therefore, an external bus driver is recommended.

Clock

The clock should be properly terminated to digital ground
near the clock input pin. Clock frequency defines the
conversion frequency and controls the converter as
described in the Theory of Operation" section. The Auto
Balance <t>1 half cycle of the clock may be reduced to 16ns;
the Sample <>2 half cycle may be varied from a minimum of
16ns to a maximum of 8ns.

TABLE 2. CHIP ENABLE TRUTH TABLE

ceT

CE2

D0-D5

OVF

Valid

Three-State

Valid

Three-State

X = Don't Care

TABLE 3. PHASE CONTROL

CLOCK

PHASE

INTERNAL GENERATION

Sample Unknown ($2)

Auto Balance (ij)1)

Auto Balance ($1)

Sample Unknown (i(i2)

Gain and Offset Adjustment

In applications where accuracy is of utmost importance,
three adjustments can be made; i.e., offset, gain, and
midpoint trim. In general, offset and gain correction can be
done in the preamp circuitry.

Offset Adjustment

The preferred offset correction method is to introduce a DC
component to V| N of the converter. An alternate method is to
adjust the V REF . input to produce the desired offset
adjustment. The theoretical input voltage to produce the first
transition is 1/2LSB.

V, N (0 to 1 transition) = 1/2LSB = 1/2(V REF /64) = V REF /128
Gain Adjustment

In general, full scale error correction can be done in the
preamp circuitry by adjusting the gain of the op amp. An
alternate method is to adjust the V REF+ input voltage. This
adjustment is performed by setting V !N to the 63 to overflow
transition. The theoretical input voltage to produce the
transition is 1/2LSB less than V REF+ and is calculated as
follows:

V| N (63 to 64 transition) = V REF - (V REF /128) = V REF (127/128).

To perform the gain trim, first do the offset trim and then
apply the required V, N for the 63 to overflow transition. Now
adjust V REF+ until that transition occurs on the outputs.

Midpoint Trim

The reference center (1/2R) is available to the user as the
midpoint of the resistor ladder. The 1/2R point can be used
to improve linearity or create unique transfer functions. The
offset and gain trims should be done prior to adjusting the
midpoint. The theoretical transition from count 31 to 32
occurs at 31 .SLSB's. That voltage is calculated as follows;

V, N (31 to 32 transition) = 31 .5(V REF /64) = V REF (63/128).

An adjustable voltage follower can be used to drive the 1/2R
pin. Set V| N to the 31 to 32 transition voltage, then adjust the
voltage follower until the transition occurs on the output bits.

Signal Source

A current pulse is present at the analog input (V, N ) at the
beginning of every sample and auto balance period. The
transient current is due to comparator charging and switch
feed through in the capacitor array. It varies with the
amplitude of the analog input and the sampling rate.

1-79

HI-S701

The signal source must be capable of recovering from the
transient prior to the end of the sample period to ensure a valid
signal for conversion. Suitable broad band amplifiers or buffers
which exhibit tow output impedance and high output drive
include the HFA-0005, HA-5004, HA-5002, and HA-5033.

The signal source may drive above or below the power
supply rails, but should not exceed 0.5V beyond the rails or
damage may occur. Input voltages of -0.5V to +1/2LSB are
converted to all zeros; input voltages of V REF+ - 1/2LSB to
V DD + 0.5 are converted to all ones with the Overflow bit set.

Power Supplies

The HI-5701 operates nominally from 5 volt supplies but will
function from 3 volts to 6 volts. The analog supply should be

well regulated and "clean" of significant noise, especially
high frequency noise. It is recommended that power supply
decoupling capacitors be placed as close to the supply pins
as possible. A combination of 0.01 uF ceramic and 10uF
tantalum capacitors is recommended for this purpose as
shown in the test circuit Figure 4.

Reducing Power Consumption

Power dissipation in the HI-5701 is related to clock frequency
and clock duty cycle. For a fixed 50% clock duty cycle, power
may be reduced by lowering the clock frequency. For a given
conversion frequency, power may be reduced by shortening
the Auto Balance $1 portion of the clock duty cycle.

TABLE 4. OUTPUT CODE TABLE

CODE
DESCRIPTION

INPUT VOLTAGE*
Vref. = 4.0V

v REF . = o.ov

(V)

DECIMAL
COUNT

MSB

BINARY OUTPUT CODE

LSB

OVF

Overflow (OVF)

4.000

127

FuH Scale (FS)

3.9375

FS-1LSB

3.875

•
•

3/4 FS

•

3.000

•
•

1/2 FS

•

2.000
•
•

1/4 FS

•

1.000
•
•

1LSB

•

0.0625

Zero

• The voltages listed above represent the ideal transition of each output code shown as a function of the reference voltage.

1-80

HI-5701

Glossary of Terms

Aperture Jitter: This is the RMS variation in the aperture
delay due to variation of internal <|>1 and $2 clock path delays
and variation between the individual comparator switching

Differential Linearity Error (DNL): The differential linearity
error is the difference in LSBs between the spacing of the
measured midpoint of adjacent codes and the spacing of
ideal midpoints of adjacent codes. The ideal spacing of
each midpoint is 1 .OLSB. The range of values possible is
from -1 .OLSB (which implies a missing code) to greater than
+1.0LSB.

Full Power Input Bandwidth: Full power bandwidth is the
frequency at which the amplitude of the fundamental of the
digital output word has decreased 3dB below the amplitude of
an input sine wave. The input sine wave has a peak-to-peak
amplitude equal to the reference voltage. The bandwidth
given is measured at the specified sampling frequency.

Full Scale Error (FSE): Full Scale Error is the difference
between the actual input voltage of the 63 to 64 code
transition and the ideal value of V REF+ - 1.5LSB. This error is
expressed in LSBs.

Integral Linearity Error (INL): The integral linearity error is
the difference in LSBs between the measured code centers
and the ideal code centers. The ideal code centers are
calculated using a best fit line through the converter's
transfer function.

LSB: Least Significant Bit = (V REF+ - V REF .)/64. All
HI-5701 specifications are given for a 62.5mV LSB size
V REF+ = 4.0V,V REF . = 0.0V.

Offset Error (VOS): Offset error is the difference between
the actual input voltage of the to 1 code transition and
the ideal value of V REF . + 0.5LSB. VOS error is expressed
in LSBs.

Power Supply Rejection Ratio (PSRR): PSRR is
expressed in LSBs and is the maximum shift in code
transition points due to a power supply voltage shift. This
is measured at the to 1 code transition point and the 62
to 63 code transition point with a power supply voltage
shift from the nominal value of 5.0V.

Signal to Noise Ratio (SNR): SNR is the ratio in dB of the
RMS signal to RMS noise at specified input and sampling
frequencies.

Signal to Noise and Distortion Ratio (SINAD): SI NAD is

the ratio in dB of the RMS signal to the RMS sum of the
noise and harmonic distortion at specified input and
sampling frequencies.

Total Harmonic Distortion (THD): THD is the ratio in dBc of
the RMS sum of the first five harmonic components to the
RMS signal for a specified input and sampling frequency.

CLOCK
INPUT

+4V |

10UF:|:

0.01 UF:

D5
OVF

CE2
CE1

PHASE

Vref.

04
D3
1/2R
02
D1
DO

Vin

Vref-

0.01 UF

T "*'T

+9V to +12V

\ D

OUPUT

-J— |+5V

• ioon

0.01 HF^ 10U.F^

i I _ ANALOG

• □ SIGNAL

INPUT

son

-9VIO-12V

U.F^ 10UF^:

FIGURE 3. TEST CIRCUIT

1-81

SEMICONDUCTOR

HI5800

PRELIMINARY

July 1992

12-Bit, 3MSPS Sampling A/D Converter

Features

• 3MSPS Throughput Rate

• 1 2-Bit, No Missing Codes over Temperature

• 1.0LSB Integral Linearity Error

• Buffered Sample and Hold Amplifier

• Precision Voltage Reference

• ± 2.5V Input Signal Range

• 20MHz Input BW Allows Sampling Beyond Nyqulst

• Zero Latency/No Pipeline Delay

Applications

• High Speed Data Acquisition Systems

• Medical Imaging

• Radar Signal Analysis

• Document and Film Scanners

• Vibration/Waveform Spectrum Analysis

• Digital Servo Control

Description

The HI5800 is a monolithic, 12-bit, sampling Analog-to-
Digital Converter fabricated in the HBC10 BiCMOS process.
It is a complete subsystem containing a sample and hold
amplifier, voltage reference, two-step subranging A/D, error
correction, control logic, and timing generator. The HI5800 is
designed for high speed applications where wide bandwidth,
accuracy and low distortion are essential.

The HI5800 is available in Commercial and Industrial tem-
perature ranges and is offered in a 40 pin Sidebraze and a
44 pin PLCC package.

Ordering Information

PART

TEMP.

NUMBER

LINEARITY

RANGE

PACKAGE

HI5800AID

±2LSB

-40°C to +85°C

40 Pin

HI5800BID

±1LSB

Sidebraze

HI5800JCM*

±2LSB

0°C to +75°C

44 Pin PLCC

HI5800KCW

±1LSB

Consult factory for availability

Pinouts

40 PIN SIDEBRAZE

TOP VIEW

44 PIN PLCC

TOP VIEW

ROadj fj
RGADjfJ

II,

■P 8 -

c < a. 2

.nnnnnnnnnn n .

- 2 1 44 43 42 41 40 \

E o 3 o a

6 S 4 3

VlN
AGND
ADJ-f
ADJ-

av ee

NC
AVcc
AGND

av ee

C ^
C *
C »
C 10
C 11
C «
C 13
C 14
C 15
C 1«
C "

16 19 20 21

TJLTLTO

DV EE [T5

DGND Qi
DV CC

S]D1

5]D0(LSB)
SJAVcc

a 5 > -

22 23 24 25 26 27 28

uuuuuuu

8 g 8 8 s a a

39 □ D9
38 □ D8
37 □ DV CC
36 □ DGND
35 □ AGND
34 3 NC
33 □ AV EE
32 D D7
31 □ D6
30 □ D5
28 □ D4

CAUTION: These devices are sensitive to electrostatic discharge Users should follow proper I.C. Handling Procedures.
Copyright © Harris Corporation 1992

File Number 2938.1

HI5800

Functional Block Diagram

REFooj
REF W

ADJ-

7 BIT
FLASH

7 BIT
LATCH

-N
V

7 BIT
LATCH

7 BIT
DAC

X32

CONTROL
LOGIC
AND
TIMING

AVcc AV EE DV CC DV EE AGND DGND

RGadj ROadj

DO(LSB)

DIGITAL
OUTPUTS

D10

D11 (MSB)
OVF

IRQ

CONV

Typical Application Schematic

C23>| »1<VF

conv -L©-

AO
CS

vcc
m

10K

RIO- '
10K>

H11
10K

(22)(LSB)DO
(23) D1

REFJN(1) P*) M
REF_OUT(5» I 25 )" 3
(26) CM
AGND V (27,05

AGND (12)

(28) D6

° G '"< 3, » (29) D7
DGM5 < , »> (34)D8
^P 2 ' <35)D9
VlM(8)

(37XMS8)Olt
(40, IRQ
(39) OVF

CONVM7)

(18) DVEE

OE (16)

AO (14) (33)DVCC
55(15,

(4) AVCC
(«)

RO_ADJ(2,

(21, AVCC
RC_ADJ(3)(M)

(10, AVEE
ADJ*(8) <«,(30,

ADJ-(9)

- D1

- 02

- D3

- D4
■ D5

- DC

- D7
• DS

- M
-D10
-D11

- IRQ
-OVF

10(1 F, 0.1(,F, AND 0.01(iF CAPS ARE PLACED
AS CLOSE TO PART AS POSSIBLE

0.01(iF

C1lJ_ |o4 J»
1 O-OImf T "F , '^[ C3310|»F

C14£ (
0.01 (iF^

C17|_

13 j*
°- 1 I^C2610|lF

1-83

Specifications HI5800

35°C/W

N/A
9°C/W

Absolute Maximum Ratings

Supply Voltages

AVcc or DV CC to GND +5.5V

AV EE or DV EE to GND -5.5V

DgndIoAqnd ±0.3V

Analog Input Pins

Reference Input REF 1N +2.75V

Signal Input V, N ±(REF 1N +0.2V)

RO ADJ , RGadj, ADJ+, ADJ- V EE to V cc

Digital I/O Pins GND to V^

Operating Temperature Range

HI5800JCM/KCM 0°C to +75°C

HI5800AID/BID -40°C to +85°C

Junction Temperature

HI5800JCM/KCM +150°C

HI5800AID/BID +175°C

Storage Temperature Range -65°C to +150°C

Lead Temperature (Soldering, 10sec) +300°C

CAUTION: Stresses above those listed in 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
ot the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Information

Thermal Resistance

HI5800JCM/KCM

HI5800AID/BID 29°C/W

Power Dissipation at +75°C (Note 1)

HI5800JCM/KCM 2.2W

HI5800AID/BID 3.5W

Power Dissipation Derating Factor Above +75°C

HI5800JCM/KCM 29mW/°C

HI5800AID/BID 35mW/°C

NOTE:

1. Dissipation rating assumes device is mounted with all leads sol-
dered to printed circuit board

Electrical Specifications AV CC = +5V, DV CC = +5V, AV EE = -5V, DV EE = -5V; Internal Reference Used.
Unless Otherwise Specified.

PARAMETER

TEST CONDITION

HI5800JCM/AID

HI5800KCM/BID

UNITS

0°C to +75°C
-40°C to +85°C

0°C to +75°C
-40°C to +85 C

MIN

TYP

MAX

MIN

TYP

MAX

SYSTEM PERFORMANCE

Resolution

Bits

Integral Linearity Error, INL

F s = 3MHz,f IN = 45Hz Ramp

±0.7

±2

±0.7

±1

LSB

Differential Linearity Error, DNL
(Guaranteed No Missing Codes)

F s = 3MHz,f IN = 45Hz Ramp

±0.5

±1

±0.4

±1

LSB

Offset Error, VOS
(Adjustable to Zero)

(Note 7)

±2

±10

±2

±10

LSB

Full Scale Error, FSE
(Adjustable to Zero)

(Note 7)

±2

±10

±2

±10

LSB

Gain Error
(Adjustable to Zero)

±2

±15

±2

±15

LSB

DYNAMIC CHARACTERISTICS (Input Signal Level 0.5dB below full scale)

Throughput Rate

No Missing Codes

3.0

MSPS

Signal to Noise Ratio (SNR)
RMS Signal

RMS Noise

F s = 3MHz, f, N = 20kHz
F s = 3MHz, f, N = 1 MHz

66
65

69
67

68
67

71
69

dBc
dBc

Signal to Noise Ratio (SINAD)
RMS Signal

RMS Noise + Distortion

F s = 3MHz, f IN = 20kHz
F s = 3MHz, f IN = 1MHz

66
65

68
67

70
68

dBc
dBc

Total Harmonic Distortion, THD

F s = 3MHz, f IN = 20kHz
F s = 3MHz,f| N = 1MHz

-74
-70

-70
-68

-82
-75

-74
-70

dBc
dBc

Spurious Free Dynamic Range,
SFDR

F s = 3MHz, f, N = 20kHz
F s = 3MHz,f IN = 1MHz

72
69

76
72

76
71

84
75

dBc
dBc

Intermodulation Distortion, IMD

F s = 3MHz, f1 = 49kHz,
f 2 = 50kHz

-74

-68

-82

-70

dBc

1-84

Specifications HI5800

Electrical Specifications AV CC = +5V, DVcc = +5V, AV EE = -5V, DV EE = -5V; Internal Reference Used.
Unless Otherwise Specified. (Continued)

HIS800JCM/AIO

HI5800KCM/BID

0°C to +75°C
-40°C to +85°C

PARAMcTcH

1 Lb 1 OUNUIMUN

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Differential Gain

F s = 1MHz

0.9

Differential Phase

F s = 1 MHz

0.05

Degree
s

Aperture Delay, t AD

Aperture Jitter, t^j

ANALOG INPUT

Input Voltage Range

±2.5

±2.7

±2.5

±2.7

Input Resistance

Mil

Input Capacitance

Input Current

±10

Input Bandwidth

MHz

INTERNAL VOLTAGE REFERENCE

Reference Output Voltage,
REFOUT (Loaded)

2.450

2.500

2.550

2.470

2.500

2.530

Volts

Reference Output Current

Note 5

Reference Temperature
Coefficient

ppnrVC

REFERENCE INPUT

Reference Input Range

2.5

2.6

2.5

2.6

Reference Input Resistance

200

DIGITAL INPUTS

Input Logic High Voltage, V| H

Note 6

2.0

Input Logic Low Voltage, V !L

0.8

Input Logic Current, l, L

V| N = OV, 5V

1.0

±10

Digital Input Capacitance, CI N

V| N = OV

5.0

DIGITAL OUTPUTS

Output Logic High Voltage,V H

i out = -' | 60uA

2.4

4.3

2.4

4.3

Output Logic Low Voltage,V OL

'out - 3-2mA

0.22

0.8

0.22

0.8

Output Logic High Current, Ioh

-0.160

Output Logic Low Current, I l

3.2

Output 3-state Leakage Current,
loz

V OUT = 0V,5V

±1

±10

±1

±10

Digital Output Capacitance, Cqut

TIMING CHARACTERISTICS

Minimum CONV Pulse, t1

(Notes 2, 3)

,»

1 ,.

I I "

1-85

Specifications HI5800

Electrical Specifications AVcc = +5V, DV CC = +5V, AV EE = -5V, DV EE = -5V; Internal Reference Used.
Unless Otherwise Specified. (Continued)

HI5800JCM/AID

HI5800KCM/BID

0°C to +75°C
-40°C to +85°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

CS to CONV Setup Time, t2

(Note 2)

CONV to CS Setup Time, t3

(Note 2)

Minimum OE Pulse, t4

(Notes 2, 4)

CS to OE Setup Time, t5

(Note 2)

OfTto CS Setup Time, t6

(Note 2)

IRQ Delay from Start Convert, t7

(Note 2)

IRQ Pulse Width, t8

190

205

230

190

205

230

Minimum Cycle Time for
Conversion, t9

333

IRQ to Data Valid Delay, t10

(Note 2)

-5

Minimum AO Pulse, t1 1

(Notes 2, 4)

•

Data Access from OE Low, t12

(Note 2)

LSB, Nibble Delay from AfjHigh,
t13

(Note 2)

MSB Delay from AO Low, 114

(Note 2)

CS to Float Delay, t15

(Note 2)

Minimum CS Pulse, t16

(Notes 2, 4)

CS to Data Valid Delay, t17

(Note 2)

Output Fall Time, tf

(Note 2)

Output Rise Time, tr

(Note 2)

POWER SUPPLY CHARACTERISTICS

IVcc

180

220

180

220

158

190

158

190

IDV CC

IDV EE

2.7

Power Dissipation

1.8

2.2

1.8

2.2

PSRR

Vcc V EE ±5%

0.01

0.05

0.01

0.05

%/%

NOTE:

2. Parameter guaranteed by design or characterization and not production tested.

3. Recommended pulse width for CONV is 60ns.

4. Recommended minimum pulse width is 25ns.

5. This is the additional current available from the REF ou t Pi" w*h the REF OUT pin driving the REF IN pin.

6. The AO pin V, H at -40°C may exceed 2.0V by up to 0.4V at initial power up.

7. Excludes error due to internal reference temperature drift.

1-86

HI5800

Timing Diagrams

IRQ

ACQUIRE N

y j^N CON VERSION N y

DATA VALID

N - 1 DATA

N DATA

D0-D11, OVF

-j ^ N DATA y ~

t17[—

FIGURE 1. SINGLE SHOT TIMING

CS-

i t \

h— — -4

t5 t6

FIGURE 2A. START CONVERSION SETUP TIME

51-

FIGURE 2B. OUTPUT ENABLE SETUP TIME

H " h

IRQ

ACQUIRE N y j^ N CONVERSION N \ ACQUIRE N ♦ 1 / <*1 CONVERSIO^

|- 19 h H0 |j

DATA VAUD

N - 1 DATA

AO.

OE .

+ 1 DATA

D0-D11.OVF.

D11-D4 YDMO^MOYDII-WX D11-D4

N DATA

N + 1 DATA

FIGURE 3. CONTINUOUS CONVERSION TIMING

1-87

HI5800

Typical Performance Curves

TYPICAL SNR vs INPUT FREQUENCY

TYPICAL THD vs INPUT FREQUENCY

3K 500K 1M 2

20K

INPUT FREQUENCY (Hi)

500K 1M
INPUT FREQUENCY (Hz)

TYPICAL SND vs INPUT FREQUENCY

TYPICAL SPDR vs INPUT FREQUENCY

80
70
60
50
40
30
20
10

20K

(Hi)

20K

500K 1M
INPUT FREQUENCY (Hi)

HI5800

Typical Performance Curves (continued)

DIFFERENTIAL NON-LINEARITY

INTEGRAL NON-LINEARITY

1.0

a °-5

-0.5

-1.0

1000

2000
CODE

FFT SPECTRAL PLOT FOR F, N = 20kHz, F s = 3MHz

-75

-135

365K 730K 1

FREQUENCY (Hz)

FFT SPECTRAL PLOT FOR F IN = 1MHz, F s = 3MHz

-25
-50

O-100

-135

FREQUENCY (Hz)

FFT SPECTRAL PLOT FOR F IN = 2MHz, F s = 3MHz

—4

INTERMODULATION DISTORTION PLOT FOR F, N = 49kHz,
50kHz at F s = 3MHz

730K 1.095M 1.'

FREQUENCY (Hz)

36.6K 55K 73.3K
FREQUENCY (Hz)

91.6K 110K

HI5800

TABLE 1. PIN DESCRIPTION

44 PIN

PLCC

40 PIN
DIP

PIN
NAME

PIN DESCRIPTION

REF| N

External reference input.

RO AD j

DAC offset adjust (Connect to AGND If not used).

RG ADJ

DAC gain adjust (Connect to AGND if not used).

AVqc

Analog positive power supply, +5 V

Internal reference output, +2.5V.

No connection.

V, N

Analog input voltage.

AGND

Analog ground.

ADJ+

Sample/hold offset adjust (Connect to AGND if not used).

ADJ-

Sample/hold offset adjust (Connect to AGND if not used).

AV ee

Analog negative power supply, -5V

AV CC

Analog positive power supply, +5V

AGND

Analog ground.

AV EE

Analog negative power supply, -5V

Output byte control input, active low. When low, data is presented as a 12 bit word or the upper byte
(D11-D4) in 8 bit mode. When high, the second byte contains the lower LSBs (D3-D0) with 4 trailing
zeroes. See Text.

Chip Select input, active low. Dominates all control inputs.

No connection.

Output Enable input, active low.

CONV

Convert start input, initiates conversion on the falling edge. If held low, continuous conversion mode
overrides and remains in effect until the input goes high.

DV EE

Digital negative power supply, -5V.

DGND

Digital ground.

DV CC

Digital positive power supply, +5V.

AV CC

Analog positive power supply, +5V.

Data bit 0, (LSB).

Data bit 1.

Data bit 2.

Data bit 3.

No connection

Data bit 4.

Data bit 5.

Data bit 6.

Data bit 7.

AV EE

Analog negative power supply, -5V.

AGND

Analog ground.

DGND

Digital ground.

DV CC

Digital positive power supply, +5 V.

Data bit 8.

Data bit 9.

No connection.

D10

Data bit 10.

D11

Data bit 11 (MSB).

AVcc

Analog positive power supply, +5V.

OVF

Overflow output Active high when either an cverrange or underrange analog input condition is detected.

IRQ

Interrupt ReQuest output. Goes low when a conversion is complete.

1-90

HI5800

Detailed Description

The HI5800 is a 12-bit two step sampling analog to digital
converter which uses a subranging technique with digital
error correction. As illustrated in the block diagram, it uses a
sample and hold front end, 7-bit R-2R D/A converter which is
laser trimmed to 14 bits accuracy, a 7-bit BiCMOS flash con-
verter, precision bandgap reference, digital controller and
timing generator, error correction logic, output latches and
BiCMOS output drivers.

The falling edge of the convert command signal puts the
sample and hold (S/H) in the hold mode and the conversion
process begins. At this point the Interrupt Request (IRQ) line
is set high indicating that a conversion is in progress. The
output of the S/H circuit drives the input of the 7-bit flash
converter through a switch. After allowing the flash to settle,
the intermediate output of the flash is stored in the latches
which feed the D/A and error correction logic. The D/A
reconstructs the analog signal and feeds the gain amplifier
whose summing node subtracts the held signal of the S/H
and amplifies the residue by 32. This signal is then switched
to the flash for a second pass using the input switch. The
output of the second flash conversion is fed directly to the
error correction which reconstructs the twelve bit word from
the fourteen bit input. The logic also decodes the overflow bit
and the polarity of the overflow. The output of the error cor-
rection is then gated through the read controller to the output
drivers. The data is ready on the bus as soon as the IRQ line
goes low.

I/O Control Inputs

The converter has four active low inputs (CS, CONV, OE and
AO) and fourteen outputs (D0-D11, IRQ and OVF). All inputs
and outputs are TTL compatible and will also interface to the
newer TTL compatible families. All four inputs are CMOS
high input impedance stages and all outputs are BiMOS driv-
ers capable of driving 100pF loads.

In order to initiate a conversion or read the data bus, CS
should be h eld low . The conversion^ initiated by the falling
edge of the CONV command. The OE input controls the out-
put bus directly and is independent of the conversion pro-
cess. The data on thebus changes just before the IRQ goes
low. Therefore if the OE line is held low all the time, the data
on the bus will change just before the IRQ line goes low. The
byte control signal AO is also independent of the conversion
process and the byte can be manipulated anytime. When AO
is low the 12 bits and overflow word is read on the bus. The
bus can also be hooked up such that the upper byte (D11 to
D4) is read when AO is low. When AO is high, the lower byte
(D3 to DO) is output on the same eight pins with trailing
zeros.

In order to minimize switching noise during a conversion,
byte manipulations done using_the AO signal should be done
in the single shot mode and AO should be changed during
the acquisition phase. For accuracy, allow sufficient time for
settling from any glitches before the next conversion.

Once a conversion is started, the converter will complete the
conversion and acquisition periods irrespective of the input
states. If during these cycles another convert command is
issued, it will be ignored until the acquire phase is complete.

Stand Alone Operation

The converter can be operated in a stand alone configura-
tion with bus inputs controlling the converter. The con version
will be started on the negative edge of the convert (CONV)
pulse as long as this pulse is less than the converter
throughput rate. If the converter is given multiple convert
commands, it will ignore all but the first command until such
time when the acquisition period of the next cycle is com-
plete. At this point it will start a new conversion on the first
negative edge of the input command. This allows the con-
verter to be synchronized to a multiple of a faster external
clock. The new output data of the conversion is available on
the same cycle at the negative edge of the IRQ pulse and is
valid until the next negative edge of the IRQ pulse. Data may
be accessed at any time during these cycles. It should be
noted that if the data bus is kept enabled all the time (OE is
low), then the data will be updating just before the IRQ goes
low. During this time, the data may not be valid for a few
nanoseconds.

Continuous Convert Mode

The conve rter can be operated at its maximum rate by taking
the CONV line low (supplying the first negative edge) and
holding it low. This enables the continuous convert mode.
During this time, at the end of the internal acquisition period,
the converter automatically starts a new conversion. The
data will be valid between the IRQ negative edges.

Note that there is no pipeline delay on the data. The output
data is available during the same cycle as the conversion
and is valid until the next conversion ends. This allows data
access to both previous and present conversions in the
same cycle.

When initiating a c onversio n or a series of conversions, the
last signal (CS and CONV) to arrive dominates the function.
The same condition holds true for enabling the bus to read
the data (CSand OE). To terminate the bus operations, the
first signal (CS and OE) to arrive dominates the function.

Interrupt Request Output

The interrupt request line (IRQ) goes high at the start of
each conversion and goes low to indicated the start of the
acquisition. During the time that IRQ is high, the internal
sample and hold is in hold mode. At the termination of IRQ,
the sample and hold switches to acquire mode which lasts
approximately 100ns. If no convert command is issued for a
period of time, the sample and hold simply remains in
acquire mode tracking the analog input signal until the next
conversion cycle is initiated. The IRQ line is the only output
that is not tristateable.

Analog Input, V IN

The analog input of the HI5800 is coupled into the input
stage of the Sample and Hold amplifier. The input is a high
impedance bipolar differential pair complete with an ESD
protection circuit. Typically it has >10M£i input impedance.
With this high input impedance circuit, the HI5800 is easily
interfaced to any type of op-amp without a requirement for a

1-91

HI5800

high drive capability. Adequate precautions should be taken
while driving the input from high voltage output op-amps to
ensure that the analog input pin is not overdriven above the
specified maximum limits. For a +2.5V reference, the analog
input range is ±2.5V. This input range scales with the value
of the external reference voltage if the internal reference is
not used. For best performance, the analog ground pin next
to the analog input should be utilized for signal return.
Voltage Reference, REF OUT

The HI5800 has a curvature corrected internal band-gap ref-
erence generator with a buffer amplifier capable of driving up
to 15mA. The band-gap and amplifier are trimmed to give
+2.50V. When connected to the reference input pin REF| N ,
the reference is capable of driving up to 2mA externally. Fur-
ther loading may degrade the performance of the output volt-
age. It is recommended that the output of the reference be
decoupled with good quality capacitors to reduce the high-
frequency noise.
Reference Input, REF IN

The converter requires a voltage reference connected to the
REF| N pin. This can be the above internal reference or it can
be an external reference. The REF| N pin is approximately
200C1 input impedance and care should be taken to ensure
that the external reference is capable of driving this input
impedance. It is also recommended that adequate high fre-
quency decoupling is provided at the reference input pin in
order to minimize overall converter noise.
Error Adjustments

For most applications the accuracy of the HI5800 is sufficient
without any adjustments. In applications where accuracy is
of utmost importance three external adjustments are possi-
ble: S/H offset, D/A offset and D/A gain. Figure 4 illustrates
the use of external potentiometers to reduce the HI5800
errors to zero.

The D/A offset (RO ADJ ) and S/H offset (ADJ+ and ADJ-)
trims adjust the voltage offset of the transfer curve while the
D/A gain trim (RG ADJ ) adjusts the tilt of the transfer curve
around the curve midpoint (code 2048). The 10K£i potenti-
ometers can be installed to achieve the desired adjustment
in the following manner.

Typically only one of the offset trimpots needs to be used.
The offset should first be adjusted to get code 2048 centered
at a desired DC input voltage such as zero volts. Next the

gain trim can be adjusted by trimming the gain pot until the
4094 to 4095 code transition occurs at the desired voltage
(2.500 - 1.5LSBs for a 2.5V reference). The gain trim can
also be done by adjusting the gain pot until the code to 1
transition occurs at a particular voltage (-2.5 + 0.5LSBs for a
2.5V reference). If a nonzero offset is needed, then the offset
pot can be adjusted after the gain trim is finished. The gain
trim is simplified if an offset trim to zero is done first with a
nonzero offset trim done after the gain trim is finished. The
D/A offset and S/H offset trimpots have an identical effect on
the converter except that the S/H offset is a finer resolution
trim. The D/A offset and D/A gain typically have an adjust-
ment range of ±30LSBs and the S/H offset typically has an
adjustment range of ±20LSBs.

If no external adjustments are required the following pins
should be connected to analog ground (AGND) for optimum
performance: RO ADJ , RG ADJ , ADJ+, and ADJ-.

(j> Vcc

ADJ+

VEEO-*

ADJ-

FIGURE 4. D/A OFFSET, D/A GAIN AND S/H OFFSET ADJUST-
MENTS.

Typical Application Schematic

Figure 5 shows a typical schematic diagram for the HI5800.
The adjust pins are shown with 10K£2 potentiometers used
for gain and offset adjustments. These potentiometers may
be left out and the respective pins should be connected to
ground for best untrimmed performance.

TABLE 2. I/O TRUTH TABLE

INPUTS

OUTPUT

FUNCTION

CONV

IRQ

No operation.

Continuous convert mode.

Outputs all 12-bits and OVF or upper byte D1 1-D4 in 8 bit mode.

In 8 bit mode, outputs lower LSBs D3-D0 followed by 4 trailing zeroes
and OVF, (See text).

Converter is in acquisition mode.

Converter is busy doing a conversion.

Data outputs and OVF in high impedance state.

X's = Don't Care

HI5800

TABLE 3. AID OUTPUT CODE TABLE

CODE
DESCRIPTION

LSB = * t Ht HN)
4096

INPUT
VOLTAGE*
REF|M - 2.5V
(V)

OUTPUT DATA (OFFSET BINARY)
MSB LSB

OVF

D11

D10

>+FS

2: +2.5000

+FS - 1 LSB

+2.49878

+3/4FS

+1.8750

+1/2FS

+1.2500

+1LSB

+0.00122

A Annn
U.UUUU

-1 LSB

-0.00122

-1/2FS

-1.2500

-3/4FS

-1.8750

-FS + 1LSB

-2.49878

<-FS

S -2.5000

* The voltages listed above represent the Ideal center of each output code shown as a function of the reference voltage.

Definitions

Static Performance Definitions

Offset, fullscale, and gain all use a measured value of the inter-
nal voltage reference to determine the ideal plus and minus
fullscale values. The results are all displayed in LSB's.
Offset Error (VOS)

The first code transition should occur at a level 1/2LSB above
the negative fullscale. Offset is defined as the deviation of the
actual code transition from this point. Note that this is adjustable
to zero.

Fullscale Error (FSE)

The last code transition should occur for a analog input that is 1
and 1/2 LSB's below positive fullscale. Fullscale error is defined
as the deviation of the actual code transition from this point.

Gain Error

Gain error is calculated by dividing the measured fullscale range
by the ideal fullscale range. Note that this is adjustable to zero.

Differential Linearity Error (DNL)

DNL is the worst case deviation of a code width from the ideal
value of 1LSB. The converter is guaranteed for no missing
codes over all temperature ranges.

Integral Linearity Error (INL)

INL is the worst case deviation of a code center from a best fit
straight line calculated from the measured data.

Power Supply Rejection (PSRR)

Each of the power supplies are moved plus and minus 5% and
the shift in the offset and gain error is noted. The number
reported is the percent change in these parameters versus
fullscale divided by the percent change in the supply.

Dynamic Performance Definitions

Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5800. A low distortion sine
wave is applied to the input, it is sampled, and the output is
stored in RAM. The data is then transformed into the frequency

domain with a 4096 point FFT and analyzed to evaluate the
dynamic performance of the A/D. The data is taken with a coher-
ent test system to avoid all the inaccuracies of having to use
window functions. The sine wave input to the part is -0.5db
down from fullscale for all these tests. All results are quoted in
dBc (decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.

Signal-to-Noise Ratio (SNR)

SNR is the measured rms signal to rms noise at a specified
input and sampling frequency. The noise is the rms sum of all of
the spectral components except the fundamental and the first
five harmonics.

Signal-to-Noise + Distortion Ratio (SINAD)

SINAD is the measured rms signal to rms sum of all other spec-
tral components below the Nyquist frequency excluding DC.

Effective Number Of Bits (ENOB)

The effective number of bits (ENOB) Is derived from the SINAD
data. ENOB is calculated from:

ENOB = (SINAD - 1.76 + Vcorr) / 6.02

where: Vcom = 0.5dB

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first 5 harmonic compo-
nents to the rms value of the measured input signal.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental rms amplitude to the rms
amplitude of the next largest spur or spectral component If the
harmonics are buried in the noise floor it is the largest peak.

Intermodulation Distortion (IMD)

Nonlinearities in the signal path will tend to generate intermodula-
tion products when two tones, f1 and f2, are present on the inputs.
The ratio of the measured signal to the distortion terms is calcu-
lated. The IMD products used to calculate the total distortion are
(f2-f1), (f2+f1), (2f1-f2), (2f1+f2), (2f2-f1), (2f2+f1), (3f1-f2), (3f1+f2),
(3f2-f1), (3f2+f1), (2f2-2f1), (2f2+2f1), (2f1), (2f2), (2f1), (2(2), (4f1),
(4f2). The data reflects the sum of all the IMD products.

1-93

SEMICONDUCTOR

HI5801

ADVANCE INFORMATION

July 1992

12-Bit, 5MSPS A/D Converter

Features

• 200ns Conversion Time

• 12-Bit No Missing Codes Over Temperature

• 0.5LSB DNL/1 .OLSB INL

• High Input Bandwidth

• Precision Voltage Reference

• ± 2.5V Input Signal Range

• Zero Latency/No Pipeline Delay

Applications

• High Speed Data Acquisition Systems

• Medical Imaging

• Radar Signal Analysis

• Document and Film Scanners

• Vibration/Waveform Spectrum Analysis

• Digital Servo Control

Description

The HI5801 is a monolithic, 12-bit, Analog-tc-Digital
Converter fabricated in the HBC10 BiCMOS process. It is a
complete subsystem containing voltage reference, two-step
subranging A/D, error correction, control logic, and timing
generator. The HI5801 is designed for high speed
applications where wide bandwidth, accuracy and low
distortion are essential.

The HI5801 is available in Commercial and Industrial tem-
perature ranges and is offered in a 40 pin ceramic DIP and a
44 pin PLCC package.

Ordering Information

PART
NUMBER

LINEARITY

TEMP.
RANGE

PACKAGE

HI5801AIJ

+2LSB

-40°C to +85°C

40PinCERDIP

HI5801BIJ

±1LSB

■40°C to +85°C

40PinCERDIP

HI5801JCM*

±2LSB

0°C to +75°C

44 Pin PLCC

HI5801KCM*

±1LSB

0°C to +75°C

44 Pin PLCC

Consult Factory for Availability

Pinout

40 PIN CERDIP

TOP VIEW

REF W [T

40] IRQ

"Oadj Li

55] ovf

RG ADJ [T

M| AV CC

AV CC LT

37] D11 (MSB)

REFour |T

36] D10

VlNF LI

35] D9

AGND |T

34] D8

VlNS [J[

33] DV CC

NC LI

32] DGND

av ee Q°

31] AGND

AV CC («

30] AV EE

AGND Q2

29] D7

AV EE [13

25] D6

AO [14

27] D5

CS Q5

26] D4

OE Qs

25] D3

CONV Q7

24] D2

dv ee 0!

23] 01

DGND [19

2] DO(LSB)

DVcc tjo

S] AVcc

Functional Block Diagram

REFout o-
REF 1N ,

o— REFERENCE | _l

V|NF<
V INS <

BIT
LATCH

RECTION |

(A
IU
X

cc
o
o

-J
h-

CC
UJ

&
o

-o D0(LSB)

-o D1

-c 02

DIGITAL

-o D10

-o D11(MSB)

-o OVF

^T'^y ^ASH [ — ^ DAC^ -

7 BIT
DAC

R°AOJ ° ° ROadj

CONTROL
LOGIC
AND
TIMING

■ IRQ
j CS
j CONV
» OE
«-o AO

AV C C AV EE DVcc DV EE AGND DGND

File Number 3287

SEMICONDUCTOR

H 158 12

July 1992

CMOS 12-Bit Sampling A/D Converter with
Internal Track and Hold

Features

• 20us Conversion Time

• 50KSPS Throughput Rate

• Built-in Track and Hold

• Guaranteed No Missing Codes Over Temperature

• Single +5V Supply Voltage

• 25m W Maximum Power Consumption

• Internal or External Clock

Applications

• Remote Low Power Data Acquisition Systems

• Digital Audio

• DSP Modems

• General Purpose DSP Front End

• uP Controlled Measurement Systems

Description

The HI5812 is a fast, low power, 12-bit successive
approximation analog-to-digital converter. It can operate
from a single 3V to 6V supply and typically draws just 1 ,9mA
when operating at 5V. The HI5812 features a built-in track
and hold. The conversion time is as low as 15us with a
5V supply.

The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through
a full conversion cycle. The output is user selectable: (i.e.)
12-bit, 8-bit (MSB's), and/or 4-bit (LSB's). A data ready flag,
and conversion-start inputs complete the digital interface.

An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.

The HI5812 is rated over the full industrial temperature
range and is offered in 24 lead narrow body Plastic Dip,
narrow body CERDIP, and wide body Plastic SOIC
packages.

Pinouts

NARROW PLASTIC DIP AND CERDIP

TOP VIEW

DROY

HI Vdo

(LSB) DO

23) 0EL

22] CLK

STRT

?2l V REF .

JEVref*

HI V| N

H Vaa *

ED V AA-

rjo

IS] OEM

u\ D11 (MSB)

Vss

13] D10

WIDE PLASTIC SOIC

TOP VIEW

DRDY | | 1

24 I |Vnn

(LSB) DO IT"?

23 | | OEL

D1|TJT

22"TI CLK

02 LXZ

FTIsTrt

MHJ

D4fJJT

lEH V R£F*

]EI]V IN

06 ITT

^11^

D7Q3

D8|~pra

15 | | OEM

D9[P?

TTTI D11 (MSB)

vss fn*

13TIP10

Ordering Information

PART
NUMBER

INL

(LSB)
(MAX
OVER
TEMP)

DNL
(BITS)
(MAX
OVER
TEMP)

TEMP. RANGE

PACKAGE

HI5812JIP

±1.5

-40°C to +85°C

24-Pin Plastic DIP

HI5812KIP

±1.0

-40°C to +85°C

24-Pin Plastic DIP

HI5812JIB

±1.5

-40°C to +85°C

24-Pin Plastic SOIC

HI5812KIB

±1.0

-40°C to +85°C

24-Pin Plastic SOIC

HI5812JIJ

±1.5

-40°C to +85°C

24-Pin CERDIP

HI5812KIJ

±1.0

-40°C to +85°C

24-Pin CERDIP

Users should follow proper I.C. Handling Procedures.
1-95

File Number 3214.1

HI5812

Functional Block Diagram

VREF+ O-

TIMING

GUIS

-<n«r

□ ecu

-eg-

H -tfc

■o 010

-O D9

-O D8

-O D7

-O D6

-O 05

-O D4

-O D3

-O 02

-O D1

-O DO(LSB)

1-96

Specifications HI5812

Absolute Maximum Ratings

Supply Voltage

V DD to Vss (Vss -0.5 V) < V DD < +6.5 V

Vaa+ to V M - (Vss -0-5 V) to (V ss +6.5 V)

Vaa+'o V od ±0.3 V

Analog and Reference Inputs

V REF (V^ -0.3 V) < Vina < (V DD +0.3 V)

Digital I/O Pins (V ss -0.3 V) < Vl/O < (V DD +0.3 V)

Operating Temperature Range

Plastic DIP, Plastic SOIC, and CERDIP -40°C to +85°C

Junction Temperature

Plastic Dip and Plastic SOIC +150°C

CERDIP +175°C

Storage Temperature Range -65°C to +150°C

Lead Temperature (Soldering, 10s) 300°C

Thermal Information

Thermal Resistance 8ja 8jc

Plastic DIP 51°C/W 21°CAV

Plastic SOIC 75°C/W 23°C/W

CERDIP 50°C/W 11°CAV

Power Dissipation at +75°C (Note 1)

Plastic DIP 1.5 W

Plastic SOIC LOW

CERDIP 2.0 W

Power Dissipation Derating Factor above +75° C

Plastic DIP 20mW/°C

Plastic SOIC 13 mW/°C

CERDIP 20mW/°C

NOTE: 1 . Dissipation rating assumes device is mounted with all
leads soldered to printed circuit board.

CAUTION: Stresses above those listed In 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Electrical Specifications v DD = v„, = sv, v REF4 . = +4.608V, Vss = v M . = v REF . = gnd, clk = External 750kHz,

Unless Otherwise Noted.

LIMITS

+25°C

-40°C to
+85°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

MIN

MAX

UNITS

ACCURACY

Resolution

Bits

Integral Linearity Error, INL
(End Point)

±1.5

LSB

±1.0

LSB

Differential Linearity Error, DNL
No Missing Codes

Bits

Gain Error, FSE
(Adjustable to Zero)

±3.0

LSB

±2.5

LSB

Offset Error, VOS
(Adjustable to Zero)

±2.0

LSB

±1.0

LSB

Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR

V BEF = 4V

V d = V A a+ = 5V±5%
V DD = V AA + = 5V±5%

0.1
0.1

±0.5
±0.5

LSB
LSB

DYNAMIC CHARACTERISTICS

Signal to Noise Ratio, SINAD
RMS Signal

f s = Internal Clock, f, N = 1kHz
f s = 750kHz, f, N = 1kHz

68.8
69.2

dB
dB

RMS Noise + Distortion

f s = Internal Clock, f, N = 1kHz
f s = 750kHz, f, N = 1kHz

71.0
71.5

dB
dB

Signal to Noise Ratio, SNR
RMS Signal

f s = Internal Clock, f, N = 1kHz
f s = 750kHz, f, N = 1kHz

70.5
71.1

dB
dB

RMS Noise

f s = Internal Clock, f IN = 1kHz
f s = 750kHz, f, N = 1kHz

71.5
72.1

dB
dB

1-97

Specifications HI5812

Electrical Specifications = v^ = sv, v REFl = +4.608V, Vss = v^. = v REF . = gnd, clk = External 750kHz,
Unless Otherwise Noted. (Continued)

PARAMETER

LIMITS

UNITS

TEST CONDITION

+25°C

-40°C to
+85°C

MIN

TYP

MAX

MIN

MAX

Total Harmonic Distortion, THD J

t s = Internal Clock, f| N = 1kHz
f s = 750kHz, f, N = 1kHz

-73.9
-73.8

dBc
dBc

f s = Internal Clock, f IN = 1 kHz
f s = 750kHz, f, N = 1kHz

-80.3
-79.0

dBc
dBc

Spurious Free Dynamic Range, J
SFDR

fs internal Clock, f IN = f kHz
f s = 750kHz, f, N = 1kHz

-75.4
-75.1

dB
dB

f s = Internal Clock, f lN = 1 kHz
f s = 750kHz, f IN = 1kHz

-80.9
-79.6

dB
dB

ANALOG INPUT

Input Current, Dynamic

AtV IN = V REF+ ,0V

±50

±100

Input Current, Static

Conversion Stopped

±0.4

±10

Input Bandwidth -3dB

MHz

Reference Input Current

160

Input Series Resistance, R s

In Series with Input Csample

420

Input Capacitance, C SAMPLE

During Sample State

380

Input Capacitance, C HOLD

During Hold State

DIGITAL INPUTS OEL, OEM, STRT

High-Level Input Voltage, V !H

2.4

Low-Level Input Voltage, V, L

0.8

Input Leakage Current, l !L

Except CLK, V IN = OV, 5V

±10

Input Capacitance, C| N

DIGITAL OUTPUTS

High-Level Output Voltage, V OH

Isource = -400uA

4.6

Low-Level Output Voltage, V 0L

Isink ■ 1 -6mA

0.4

Three-state Leakage, l 02

Except DRDY, V 0UT = OV, 5V

±10

Output Capacitance, C OU t

Except DRDY

CLOCK

High-Level Output Voltage, V 0H

Isource = -100uA (Note 2)

Low-Level Output Voltage, V 0L

lsi NK = 100uA(Note2)

Input Current

CLK Only, V, N = OV, 5V

±5

1-98

Specifications HI5812

Electrical Specifications v D0 = = sv, v REF . = +4.608V, Vss = v^. = v BEF . = gnd, clk = External 750kHz,
Unless Otherwise Noted. (Continued)

LIMITS

+25°C

-40°Cto
+85°C

PARAMETER

TEST CONDITION

MIN

TYP

MAX

MIN

MAX

UNITS

TIMING

Conversion Time (tconv + t AC o)
(Includes Acquisition Time)

Clock Frequency

Internal Clock, (CLK = Open)

200

300

400

150

500

kHz

External CLK (Note 2)

0.05

1.5

0.05

1.5

MHz

Clock Pulse Width, t LOW , t H i GH

External CLK (Note 2)

100

Aperture Delay, t D APR

(Note 2)

Clock to Data Ready Delay, t D1 DRDY

(Note 2)

105

150

180

Clock to Data Ready Delay, t D2 DRDY

(Note 2)

100

160

195

Clock to Data Ready, t DATA

(Note 2)

110

135

Start Removal Time, t R STRT

(Note 2)

-75

Start Setup Time, t su STRT

(Note 2)

100

Start Pulse Width, t w STRT

(Note 2)

Start to Data Ready Delay, t D3 DRDY

(Note 2)

105

120

Clock Delay from Start, t D STRT

(Note 2)

Output Enable Delay, t EN

(Note 2)

Output Disabled Delay, t D | S

(Note 2)

120

POWER SUPPLY CHARACTERISTICS

Supply Current, l DD + Iaa

1.9

NOTE:

2. Parameter guaranteed by design or characterization, not production tested.

1-99

HI5812

Timing Diagrams

/ V HOLD N / \

VlN 1 TRACK N \ H £ TRACK N + 1 V

OEL = OEia=V ss

FIGURE 1. CONTINUOUS CONVERSION MODE

FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK

1-100

HI5812

Timing Diagrams (Continued)

15 1 2 3 4 5

FIGURE 5. GENERAL TIMING LOAD CIRCUIT

1-101

HI5812

Typical Performance Curves

INL vs TEMPERATURE

■ V AA

+ * 5\

— i

. V REF

■ ■ l
+ = 4.

508V

A. CLK * INTERNAL

B. CLK = 750kHz

C. CLK s 1 MHz

-60 -40 -20 20 40 60 80 100 120 140
TEMPERATURE (°C)

OFFSET VOLTAGE vs TEMPERATURE

-60 -40 -20 20 40 60 80 100 120 140
TEMPERATURE (°C)

DNL VS TEMPERATURE

ACCURACY vs REFERENCE VOLTAGE

0.75

g 0-5
S
E
u

Q 0.25

♦ = 5V

.Vref

>08V

m B

m A

A. C

B. (

:lk =
:lk s
:lk =

NTER
7S0kH
1MHz

NAL
z

I I I

-60 -40 -20

80 100 120 140

VDO'
CLK

= W
= 750kH

= 5V,T A
z

= 25°C

FSE

DNL

INL

VOS

3.2 3.4 3.6 3.8 4 4.2
REFERENCE VOLTAGE, V REF (V)

FULL SCALE ERROR vs TEMPERATURE

S 1

d = v a

1EF* =

A*''-
4.608

V,
V

A.
B.

CLK =
CLK =
CLK =

INTE
750k
1MHl

RNAL

„ C

" B

■ A

-60 -40 -20 20 40 60 80 100 120 140
TEMPERATURE <°C)

POWER SUPPLY REJECTION vs TEMPERATURE

0.5

0.375

ii 0.25

0.125

Vdo = v»a+ » sv ±5%

CLK = 750kHz
V REF , = 4.0V

-20 20 40 60 80 100 120 140
TEMPERATURE (°C)

1-102

HI5812

Typical Performance Curves

SUPPLY CURRENT vs TEMPERATURE

E.
8

Vdo - V M + . 5V, V REFt . 4.608V

INTERNAL CLOCK

) 20 40 60 80 100 120 140
TEMPERATURE (°C)

0.0-
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0

FFT SPECTRUM

INPUT FREQUENCY a 1 kHz
SAMPLING RATE ■ 50kHz
SNR = 72.1dB
SINAD-71.4dB
EFFECTIVE BITS « 11.5
THD = -79.1dBc
PEAK NOISE ■ -80.9dB
SFDR = -80.9dB

::w , „

:.rr:. r im

i v i 'in!

500 1000 1500

FREQUENCY BINS

INTERNAL CLOCK FREQUENCY vs TEMPERATURE

500

EFFECTIVE BITS vs INPUT FREQUENCY

450
400

350
300
250
200
150

Vdd

t = 5V

Vbef

. = 4.

S08V

-60 -40 -20 20 40 60 80 100 120 140
TEMPERATURE (°C)

T A = 25°C

A. CLK = INTERNAL
8 -|- B. CLK • 750kHz
C. CLK = 1 MHz

0.1

1 10
INPUT FREQUENCY (kHz)

100

TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY
-80

SIGNAL-NOISE RATIO vs INPUT FREQUENCY

v D d = Vaa* = sv

V REF + ■ 4.608V
T A = 25°C

A. CLK -INTERNAL

B. CLK = 750kHz

C. CLK = 1 MHz

1 10
INPUT FREQUENCY (kHz)

100

INPUT FREQUENCY (kHz)

1-103

HI5812

TABLE 1. PIN DESCRIPTION

PIN*

NAME

DESCRIPTION

DRDY

Output flag signifying new data is available. Goes
high at end of clock period 1 5. Goes low when
new conversion is started.

Bit (Least significant bit, LSB)

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

Vss

Digital ground, (0V).

D10

Bit 10

D11

Bit 1 1 (Most significant bit, MSB)

OEM

Three-state enable for D4-D11 . Active low input.

Vaa-

Analog ground, (0V).

Vaa+

Analog positive supply. (+5V) (See text)

V,n

Analog input.

V REF +

Rpfprprw~p vnltflnp nn^itivp inni it Qpte 4nQR

code end of input range.

V REF

Rpfprpripp unltanp npnativp in n i it <*Ate rorlp
end of input range.

STRT

Start conversion input active low, recognized

aftor onrt r\f clrw~ , k norinrl 1 ^
aiici ci iu ui LsiLA«r\ pci iuu i-j.

CLK

CLK input or output. Conversion functions are
synchronized to positive going edge. (See text)

oeI

Three-state enable for DO - D3. Active low input.

Vdd

Digital positive supply (+5V).

Theory of Operation

HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that
uses capacitor-charge balancing to successively
approximate the analog input. A binarily weighted capacitor
network forms the A/D heart of the device. Page 2 shows
an illustration of the block diagram for the HI5812.

The capacitor network has a common node which is
connected to a comparator. The second terminal of each
capacitor is individually switchable to the input, V REF + or
Vrep-

During the first three clock periods of a conversion cycle, the
switchable end of every capacitor is connected to the input
and the comparator is being auto-balanced at the capacitor
common node.

During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V REF+ terminal; and the remaining
capacitors to V REF -. The capacitor-common node, after the
charges balance out, will indicate whether the input was
above V 2 of (V REF + - V REF -). At the end of the fourth period,
the comparator output is stored and the MSB capacitor is
either left connected to V REF + (if the comparator was high)
or returned to V REF -. This allows the next comparison to be
at either 3 / 4 or V 4 of (V REF + - V REF -).

At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V REF + or at V REF -.

At the end of the 15th period, when the LSB (DO) capacitor is
tested, (DO) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.

Analog Input

The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5uA and 20pF.

At the start of input tracking, clock period 1 , some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period as shown in Figure 6. The amount
of charge is dependent on supply and input voltages. The
average current is also proportional to clock frequency.

Conditions: V DD * = 5.0V, V REF , = 4.608V,

V, N = 4.608V, CLK = 750kHz, T A = +25°C

FIGURE 6. TYPICAL ANALOG INPUT CURRENT

1-104

HI5812

As long as these current spikes settle completely by end of
the signal acquisition period, converter accuracy will be
preserved. The analog input is tracked for 3 clock cycles.
With an external clock of 750kHz the track period is 4ns.

A simplified analog input model is presented in Figure 7.
During tracking, the A/D input (V !N ) typically appears as a
380pF capacitor being charged through a 420£1 internal
switch resistance. The time constant is 160ns. To charge
this capacitor from an external "zero £1" source to 0.5LSB
(1/8192), the charging time must be at least 9 time
constants or 1.4ns. The maximum source impedance
( r source Max ) ,or a 4 ^ s acquisition time settling to within
0.5LSB is 750£1

If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.

V IN R sw . 420C1

|-Vv^ □ °-6 Wv 1

dp CsAMPLf - 38»PF

"source I

Rsource (max) = ' ACQ ... ,. -"sw

C SA „ PUE ln[^»1)]

FIGURE 7. ANALOG INPUT MODEL IN TRACK MODE

Reference Input

The reference input V REF + should be driven from a low
impedance source and be well decoupled.

As shown in Figure 8, current spikes are generated on the
reference pin during each bit test of the successive approxi-
mation part of the conversion cycle as the charge-balancing
capacitors are switched between V REF - and V REF + (clock
periods 5-14). These current spikes must settle completely
during each bit test of the conversion to not degrade the
accuracy of the converter. Therefore V REF + and V REF -
should be well bypassed. Reference input V REF - is normally
connected directly to the analog ground plane. If V REF - is
biased for nulling the converters offset it must be stable
during the conversion cycle.

2|i»/Div.

Conditions: V DD = V^. = 5.0V, V REF , = 4.608V,

V, N = 2.3V, CLK = 750kHz, T A = +25°C

FIGURE 8. TYPICAL REFERENCE INPUT CURRENT

The HI5812 is specified with a 4.608V reference, however, it
will operate with a reference down to 3V having a slight
degradation in performance. A typical graph of accuracy vs
reference voltage is presented.

Full Scale and Offset Adjustment

In many applications the accuracy of the HI5812 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.

The V REF + and V REF - pins reference the two ends of the
analog input range and may be used for offset and full scale
adjustments. In a typical system the V REF - might be returned
to a clean ground, and the offset adjustment done on an
input amplifier. V REF + would then be adjusted to null out the
full scale error. When this is not possible, the V REF - input can
be adjusted to null the offset error, however, V REF - must be
well decoupled.

Full scale and offset error can also be adjusted to zero in the
signal conditioning amplifier driving the analog input (V, N ).

Control Signal

The H 1581 2 may b e synchronized from an external source
by using t he ST RT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.

The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
place. After the start of the next period 1 (specified by T D
data), the output is updated.

The DRDY (Data Ready) status output goes high (specified
by T D iDRDY) after the start of clock period 1, and returns
low (specified by T 02 DRDY) after the start of clock period 2.

The 12 data bits are available in pa rallel on three-state bus
driver outputs. When low, the OEM input enabl es the most
significant byte (D4 through D11) while the OEL input
enables the four least significant bits (DO - D3). T EN and T D , S
specify the output enable and disable times.

If the output data is to be latched externally by the DRDY
signal, the trailing edge of DRDY should be used: there is no
guaranteed setup time.

When STRT input is used to initiate conversions, operation is
slightly different depending on whether an internal or
external clock is used.

Figure 3 illustrates operation with an interna l clock. If the
STRT signal is removed (at least T R STRT) before clock
period 1 , and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.

A low signal applied to STRT (at lea st T W S TRT wide) can
now initiate a new conversion. The STRT signal (after a
delay of (T D CLK) cause the clock to restart.

Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.

1-105

HI5812

The input will continue to track until the end of period 3, the
same as when free running.

Figure 2 illustrat es the same operation as abo ve but with an
external clock. If STRT is removed (at le ast T R S TRT) before
clock period 2, a low signal applied to STRT will drop the
DRDY flag as before, and with t he first positive-going clock
edge that meets the (T SU STRT) setup time, the converter
will continue with clock period 3.

Clock

The HI5812 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are synchro-
nized with the rising edge of the clock signal.

Figure 9 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.

The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.

If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minium frequency shown in the specifications.
In the above two cases, a further restriction applies in that
the clock should not be shut off during the third sample
period for more than 1ms. This might cause an internal
charge-pump voltage to decay.

If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.

An external clock must also meet the minimum Tlow and
Thigh times shown in the specifications. A violation may
cause an internal miscount and invalidate the results.

OPTIONAL
EXTERNAL
CLOCK

ENABLE
CLOCK

— V*

lookn 2

18pF

II 1

FIGURE 9. INTERNAL CLOCK CIRCUITRY

Power Supplies and Grounding

V DD and V ss are the digital supply pins: they power all
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V 0D and V ss
lines, V ss should have a low impedance path to digital
ground and V 0D should be well bypassed.

Except for V^t, which is a substrate connection to V u d, all
pins have protection diodes connected to V DD and V ss . Input
transients above V D0 or below V ss will get steered to the
digital supplies.

The V M + and V^- terminals supply the charge-balancing
comparator only. Because the comparator is auto-balanced
between conversions, it has good low-frequency supply
rejection. It does not reject well at high frequencies however;
Vaa- should be returned to a clean analog ground and V M +
should be RC decoupled from the digital supply as shown in
Figure 10.

There is approximately 50£J of substrate impedance
between V DD and V^+. This can be used, for example, as
part of a low-pass RC filter to attenuate switching supply
noise. A 10u,F capacitor from V^a+ to ground would
attenuate 30kHz noise by approximately 40dB. Note that
back-to-back diodes should be placed from V 0D to V^* to
handle supply to capacitor turn-on or turn-off current spikes.

Dynamic Performance

Fast Fourier Transform (FFT) techniques are used to evalu-
ate the dynamic performance of the A/D. A low distortion
sine wave is applied to the input of the A/D converter. The
input is sampled by the A/D and its output stored in RAM.
The data is than transformed into the frequency domain with
a 4096 point FFT and analyzed to evaluate the converters
dynamic performance such as SNR and THD. See typical
performance characteristics.

Signal-To-Noise Ratio

The signal to noise ratio (SNR) is the measured rms signal
to rms sum of noise at a specified input and sampling
frequency. The noise is the rms sum of all except the
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N + 1.76)
dB. For an ideal 12-bit converter the SNR is 74dB. Differen-
tial and integral linearity errors will degrade SNR.

SNR = 10 log

Sinewave Signal Power
Total Noise Power

Signal-To-Noise + Distortion Ratio

SINAD is the measured rms signal to rms sum of noise plus
harmonic power and is expressed by the following.

SINAD = 10 log

Sinewave Signal Power

Noise + Harmonic Power (2nd - 6th)
Effective Number of Bits

The effective number of bits (ENOB) is derived from the
SINAD data;

ENOB :

SINAD - 1.76
a02

1-106

HI5812

Total Harmonic Distortion

The total harmonic distortion (THD) is the ratio of the rms
sum of the second through sixth harmonic components to
the fundamental rms signal for a specified input and
sampling frequency.

Total Harmonic Power (2nd - 6th Harmonic)

THD = 10 log

Sinewave Signal Power

Spurious-Free Dynamic Range

The spurious-free dynamic range (SFDR) is the ratio of the
fundamental rms amplitude to the rms amplitude of the next
largest spur or spectral component. If the harmonics are
buried in the noise floor it is the largest peak.

Sinewave Signal Power

SFDR = 10 log —

Highest Spurious Signal Power

TABLE 3. CODE TABLE

CODE
DESCRIPTION

INPUT VOLTAGE*
V REF . = 4.608V
W-0.0V
00

DECIMAL
COUNT

MSB

BINARY OUTPUT CODE

LSB

D11

D10

Full Scale (FS)

4.6069

4095

FS - 1 LSB

4.6058

4094

3/4 FS

3.4560

3072

1/2 FS

2.3040

2048

1/4 FS

1.1520

1024

1 LSB

0.001125

Zero

• The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.

+5V

Vref

^ 10nF ^ 0.1|iF 1= 0.01(iF

V V V

d= 4.7[iF d= 0.1nF ^ 0.001 jiF

V V V

ANALOG
INPUT

Vaa

vref*

v,n

-w — t — i 1

VOD
D11

DRDY
OEM

oil

STRT

CLK |o

Vref- W Vgj

OUTPUT
□ATA

750kHz CLOCK

V +

FIGURE 10. GROUND AND SUPPLY DECOUPLING

1-107

July 1992

Features

• This Circuit is Processed in Accordance to Mil-Std-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.

• 5ns Conversion Time

• 8-Channel Input Multiplexer

• 200,000 Channels/Second Throughput Rate

• Over 9 Effective Bits at 20kHz

• No Offset or Gain Adjustments Necessary

• Analog and Reference Inputs Fully Buffered

• On-Chip Track and Hold Amplifier

• uP Compatible Interface, 2's Complement Data Output

• 150mW Power Consumption

• Single 2.5V Reference Required for a ±2.5V Input Range

• Out-of-Range Rag

Applications

• uP Controlled Data Acquisition Systems

• DSP

- Avionics

- Sonic

• Process Control

• Automotive Transducer Sensing

- Industrial

• Robotics

• Digital Communication

8-Channel, 10-Bit, High Speed
Sampling A/D Converter

Description

The HI-71 53/883 is an 8-channel high speed 10 bit A/D con-
verter which uses a Two Step Flash algorithm to achieve
throughput rates of 200kHz. The converter features an 8-
channel CMOS analog multiplexer with random channel
addressing. A unique switched capacitor technique allows a
new input voltage to be sampled while a conversion is taking
place.

Internal high speed CMOS buffers at both the analog and
reference inputs simplifies interface requirements.

A Track and Hold amplifier is included on the chip, consisting
of two high speed amplifiers and an internal hold capacitor
which reduces external circuitry.

Microprocessor bus interfacing is simplified by the use of
standard Chip Select, Read and Write control signals. The
digital three-state outputs are byte organized for bus inter-
face to 8 to 16 bit systems. An Out-of-Range pin, together
with the MSB bit, can be used to indicate an under or over-
range condition.

The HI-71 53/883 operates with ± 5V supplies. Only a single
+2.5V reference is required to provide a bipolar input range
from -2.5V to +2.5V.

Ordering Information

PART
NUMBER

UNEARrTY
(MAX ILE)

TEMPERATURE
RANGE

PACKAGE

HI1-7153S/883

±1.0LSB

-55°Cto+125°C

40 Pin Ceramic
DIP

Pinout

Vref
AG

AfNO
A IN1
A|N2
A|N3
A|N4
*IN5
A IN6
A|N7
NC
TEST
AO
A1
A2
ALE
WR

RD
SMODE

40 PIN
CERAMIC DIP

TOP VIEW

35] V-

39j GND

38j V*

37] OVR

36] D9 (MSB)
35] 08

34j D7

33] D6

32] DS

31] D4

30j D3

29j 02

28] D1

27] DO (LSB)

U HOLD

25] EOC

24] DG

23] CLK

22] HBE

2f| BUS

Functional Diagram

(REF+)

INPUT

TRACK

BUFFER

AND

AMP

HOLD

! D

HI 00

BUS

OVR
D9

DATA
OUTPUTS

BUS

POWER
SUPPLY
DISTRIBUTION

TEST

V+ V- GND DG

o
o
o

EOC
HOLD
RD
WR

5§

SMODE

SET

CLK

File Number 3285

HI-7153/883

Pin Descriptions

DIM *

V REF

Reference voltage input (+2.5V).

Analog ground reference (0V).

Analog input channel 0.

*(N1

Analog input channel 1 .

A IN2

Analog input channel 2.

A|N3

Analog input channel 3.

*IN4

Analog input channel 4.

*IN5

Analog input channel 5.

A| N «

Analog input channel 6.

A)N7

Analog input channel 7.

No connect or tie to V+ only.

TEST

Test pin. Connect to DG for normal
operation.

Mux address input. (LSB) Active high.

Mux address input. Active high.

Mux address input. (MSB) Active
high.

ALE

Mux address enable. When high, the
latch is transparent. Address data is
latched on the falling edge.

Write input. With CS low, starts con-
version when pulsed low; continuous
conversions when kept low.

Chip select input. Active low

Read input. With CS low, enable out-
put buffers when pulsed low; outputs
updated at the end of conversion.

SMODE

Slow memory mode input. Active
high.

BUS

Bus select input. High = all inputs en-
abled together DO - D9, OVR Low =
Outputs enabled by HBE.

HBE

Byte select (HBE/LBE) input for 8-bit
bus. High = High byte selece, DO - D7.

CLK

Clock input, TTL compatible.

Digital ground (0V).

PIN *

SYMBOL

DESCRIPTION

EOC

End-of-co inversion status. Pulses
high at the end-of-conversion.

HOLD

Start of conversion status. Pulses low
dt ine HBnrUrvDnvvrenjn.

nn
uu

Dll U (LoDJ.

Bit 1

Oil Oi itni rt
Dll c. (JUipUl.

on
OU

Dit Q Data
Dll O Utild.

u**

nit A Rile
Dll H DIIS.

Bit 5.

Bit 6.

Bit 7.

Bit 8.

Bit 9 (MSB).

OVR

Out of Range flag. Valid at end of con-
version when output exceeds full
scale.

V+

Positive supply voltage input (+5V).

GND

Ground return for comparators (0V).

V-

Negative supply voltage input (-5V).

Multiplexer Channel Selection

ADDRESS & CONTROL INPUTS

ANALOG CHANNEL

ALE

SELECTED

A,N0

*IN1

A IN2

A|N3

A IN4

A IN5

A IN6

A IN7

1-109

HI-7153/883

Truth Tables

SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+)

BUS

HBE

ALE

FUNCTION

Initiates a conversion.

Selects mux channel. Address data is latched on falling edge of ALE. Latch
is transparent when ALE is high.

Disables all chip commands.

Enables DO - D9 and OVR.

Low byte enable: DO - D7

High byte enable: D8 - D9, OVR.

Disables all outputs (high impedance).

NOTE: X = don't care.

FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG)

BUS

HBE

ALE

FUNCTION

Continuous conversion, WR may be tied to DG.

Selects mux channel. Address data is latched on falling edge of ALE. Latch
is transparent when ALE is high.

Disables all chip commands.

Enables DO - D9 and OVR.

Low byte enable: DO - D7

High byte enable: D8 - D9, OVR.

Disables all outputs (high impedance).

NOTE: X = don't care.

DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR = RD = DG))

BUS

HBE

ALE

FUNCTION

Selects mux channel. Address data is latched on falling edge of ALE. Latch
is transparent when ALE is high.

Enables DO - D9 and OVR.

Low byte enable: DO - D7

High byte enable: D8 - D9, OVR.

NOTE: X = don't care.

1-110

Specifications HI-7153/883

Absolute Maximum Ratings

Supply Voltage

V+ to GND (DG/AG/GND) -0.3V < V+ <+5.7V

V- to GND (DG/AG/GND) -5.7V < V- <+0.3V

Analog and Reference Inputs

A,no-A in7 , V BEF (G^D-OJVJj^V^ < (V+ +0.3V)

Digital I/O Pins D0-D9, OVR, CLK, CS, RD, WR, ALE, SMODE,
HOLD, EOC, HBE, BUS, A0-A2, TEST(DG -0.3V) < V„ < (V. +0.3V)

Operating Temperature Range -55°C to +125°C

Junction Temperature +175°C

Storage Temperature Range -65°C to +150°C

Lead Temperature, (Soldering 10 sec) 300°C

ESD Classification Class 1

Thermal Information

Thermal Resistance eja Bjc

HI-7153/883 26°CAV 10°CAV

Power Dissipation at +75°C (Note 1)

HI-7153/883 3.9W

Power Dissipation Derating Factor Above +75°C

HI-7153/883 39mW/°C

Reliability Information

Transistor Count 1460

Worst Case Density 2.5 x 10 4 A/cm 2

NOTE:

1. Dissipation rating assumes device is mounted with all leads sol-
dered to printed circuit board.

CAUTION: Stresses above those listed in 'Absolute Maximum Ratings - may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: V+ = 5V, V- = -5V, V REF = 2.50V, f CLK = 600kHz with t„ = t F s 25ns and 50% Duty Cycle, Unless Otherwise Specified.

SYMBOL

DC PARAMETER

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNIT

MIN

MAX

ACCURACY

ILE

Integral Linearity Error
(Best Fit Line)

+25°C

±1.0

LSB

2,3

+125°C, -55°C

±1.0

LSB

DLE

Differential Linearity Error

+25°C

±1.0

LSB

2,3

+125°C, -55°C

±1.0

LSB

Vos

Bipolar Offset Error

+25°C

±2.5

LSB

2,3

+125°C, -55°C

±3.0

LSB

FSE

Unadjusted Gain Error

+25°C

±2.5

LSB

2,3

+125°C, -55°C

±3.0

LSB

ANALOG MULTIPLEXER

IBI

Input Leakage Current

A, N = ±2.50V

+25°C

±100

2,3

+125°C, -55°C

±100

RpSfON)

MUX On-resistance

l 1N = 100uA

+25°C

2.5

2,3

+125°C, -55°C

2.5

REFERENCE INPUT

IBR

Reference Input Bias Current

V REF = +2.50V

+25°C

±100

2,3

+125°C, -55°C

±100

LOGIC INPUTS

V,H

Input High Voltage

+25°C

2.4

2,3

+125°C, -55°C

2.4

V,L

Input Low Voltage

+25°C

0.8

2,3

+125°C, -55°C

0.8

IIL

Logic Input Current

V| N = 0V, +5V

+25°C

±1

2,3

+125°C, -55°C

±1

1-111

Specifications HI-7153/883

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Tested at: V+ = 5V, V- = -5V, V BEF = 2.50V, f CLK = 600kHz with tp, = t F < 25ns and 50% Duty Cycle, Unless Otherwise Specified.

SYMBOL

DC PARAMETER

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNIT

MIN

MAX

LOGIC OUTPUTS

V 0H

Output High Voltage

l 0H = -200uA

+25°C

2.4

2,3

+125°C, -55°C

2.4

Vol

Output Low Voltage

l OL = 1.6mA

+25°C

0.4

2,3

+125°C, -55°C

0.4

Iol

Output Leakage Current

RD = +5V,V OUT = 5V,
OV (Note 11)

+25°C

±1

2,3

+125°C, -55°C

±10

POWER SUPPLY VOLTAGE RANGE

V+

Positive Supply

Functional operation
only. (Note 10)

+25°C

4.5

5.5

8A, 8B

+125°C, -55°C

4.5

5.5

V-

Negative Supply

Functional operation
only. (Note 10)

+25°C

-4.5

-5.5

8A, 8B

+125°C, -55°C

-4.5

-5.5

POWER SUPPLY REJECTION

FSE

V+, V- Gain Error

V+ = 5V, V- = -4.75V,
-5.25V

+25°C

±0.5

LSB

2,3

+125°C, -55°C

±0.8

LSB

V- = -5V, V+ = 4.75V,
5.25V

+25°C

±0.5

LSB

2,3

+125°C, -55°C

±0.8

LSB

VOS

V+, V- Offset Error

V+ = 5V, V- = -4.75V,
-5.25V

+25°C

±0.5

LSB

2,3

+125°C, -55°C

±0.8

LSB

V- = 5V, V+ = 4.75V,
5.25V

+25°C

+0.5

LSB

2,3

+125°C, -55°C

±0.8

LSB

SUPPLY CURRENT

V+ Supply Current

V+ = 5V, V- = 5V

+25°C

2,3

+125°C, -55°C

I-

V- Supply Current

V+ = 5V, V- = 5V

+25°C

-15

2,3

+125°C, -55°C

-15

TABLE 2. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: V+ = 5V, V- = -5V, V REF = 2.50V, f CLK = 600kHz with If, = t F < 25ns and 50% Duty Cycle, Unless Otherwise Specified.

SYMBOL

AC PARAMETERS

CONDITIONS

GROUP A
SUBGROUP

TEMPERATURE

LIMITS

UNITS

MIN

MAX

tsps

Continuous Conversion Time

(Note 3)

+25°C

10, 11

+125°C, -55°C

1-112

HI-7153/883

TABLE 3. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Characterized at: V+ = 5V, V- = -5V, V BEF = 2.50V, f CLK = 600kHz with tp, = tp < 25ns and 50% Duty Cycle, Unless Otherwise Specified.

SYMBOL

PARAMETER

NOTES

TEMrcnATUHC

LIMITS

1 IMITC
UNI 1 3

MIN

MAX

tsps

Continuous Conversion Time

3,5

+25°C

+125°C, -55°C

•COW

Conversion Time, First Conversion

2,5

+25°C

4tc LK +0.63

+125°C, -55°C

4tcLK+0.8

•alew

ALE Pulse Width

+25°C

+125°C, -55°C

Address Setup Time

+25°C

+125°C, -55°C

t»H

Address Hold Time

+25°C

+125°C, -55°C

•WRL

WR Pulse Width

+25°C

100

+125°C, -55°C

100

'wREOC

WR to EOC Low

2, 4,5

+25°C

130

+125°C, -55°C

160

'hold

WR to HOLD Delay

2,5

+25°C4

150

+125°C, -55°C

170

•CKHR

Clock to HOLD Rise Delay

2, 5

+25°C

150

450

+125°C, -55°C

120

500

<CKHF

Clock to HOLD Fall Delay

3,5

+25°C

200

+125°C, -55 C

225

tcKEOC

Clock to EOC High

2,5

+25°C

630

+125°C, -55°C

800

tDATA

to DATA change

3,5

+25°C

100

350

+125°C, -55°C

400

tcD

~CS to DATA

+25°C

+125°C, -55°C

t*D

HBE to DATA

+25°C

+125 C, -55 U C

•rd

RD LO to Active

5,7

+25°C

100

+125°C, -55°C

125

RD HI to Inactive

5,8

+25°C

+125°C, -55°C

1-113

Specifications HI-7153/883

TABLE 3. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Characterized at: V+ = 5V, V- = -5V, V REF ■ 2.50V, = 600kHz with ^ = tf < 25ns and 50% Duty Cycle, Unless Otherwise Specified.

SYMBOL

PARAMETER

NOTES

TEMPERATURE

LIMITS

UNITS

MIN

MAX

Output Rise Time

5,6

+25°C

+125°C, -55°C

Output Fall Time

5,6

+25°C

+125°C, -55°C

NOTES'.

2. Slow memory mode timing.

3. Fast memory or DMA mode of operation, except the first conversion which is equal to tcoNv

4. Maximum specification to prevent multiple triggering with .

5. All input drive signal are specified with tr = tf < 10ns and shall swing from 0.4V to 2.4V for all timing specifications. A signal is considered to
change state as it crosses a 1 .4V threshold (except tRD & tRX).

6. tf, and tp load is C L = 100pF (including stray capacitance) to DG and is measured from the 10% - 90% point.

7. tRD is the time required for the data output level to change by 1 0% in response to crossing a voltage level of 1 .4V. High-Z to V OH is measured
with R L = 2.5KA and C L =10pF (including stray to DG).

8. tnx is the time required for the data output level to change by 1 0% in response to crossing a voltage level of 1 .4V. V OL to High-Z is mea-
sured with R L = 2.5K£1 to V+ and C L = 10pF (including stray to DG).

9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These pa-
rameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characteriza-
tion based upon data from multiple production runs which reflect lot to lot and within lot variation.

10. Functionality is guaranteed by negative gain error test to ±4LSB.

1 1 . Applies to all outputs which three state.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

MIL-STD-883 TEST REQUIREMENTS

SUBGROUPS (SEE TABLES 1 & 2)

Interim Electrical Parameters (Pre Burn-IN)

1,7,9

Final Electrical Test Parameters

T, 2, 3, 7, 8A, 8B, 9,10,11

Group A Test Requirements

1,2,3,7,8A, 8B, 9, 10, 11

Groups C & D Endpoints

* PDA applies to Subgroup 1 only. No other subgroups are included in PDA

1-114

HI-7153/883

Timing Waveforms

CLOCK
CS

WR \ (WR MAY BE WIRED LOW)

-<SP8

HOLD

|-«— »HOLD

TRACK \ HOLD N / TRACK N + 1 \ H0LDNt1 / TRACK N + 2 \ HOLDN , 2 f

TRACK N + 3

INTERNAL
DATA

DO - D9, OVR ...
DATA

'alew

N + 1 DATA

«DATA_»-| |^—

+ 3 ADDRESS

N DATA

N + 1 DATA

\ f

tAD

|-*-<RX

N V\ >^ N

ATA \ D,

LOW HIGH
BYTE BYTE

1 + 1
DATA

LOW

FIGURE 1. FAST MEMORY MODE (8-BIT DATA BUS)

CLOCK

ALE.

AO- A2-
HOLD

INTERNAL
DATA

D0-D9.OVR
DATA

'AS_ I 'ah

_/7T»Taddress\_

TRACK N

N +2 ADDRESS

N + 3

HOLD N

J TRACK N + 1 \ ^HOLDN + iy TRACK N + 2 ^ HOLD N + 2 j ~
»~\ |-« 'DATA

N-1 DATA

N DATA

\S N + 1 DATA

N • 1 DATA

N DATA

N + 1 DATA

CONDITIONS: SMODE ■ V+, CS ■ WR = RD = DG, BUS s V+. HBE = DG OR V+
NOTE: ECO OUTPUT IS LOW CONTINUOUSLY.

FIGURE 2. DMA MODE (16-BIT DATA BUS)

1-115

HI-7153/883

Timing Waveforms (continued)

A0-A2

HOLD

INTERNAL
DATA

RD
EOC

D0-D9.OVR
DATA

f— tax

— H h* - uiew

'hold

TRACK N

N-1 DATA

CONDITIONS: SMODE ■ V*, BUS ■ V*. HBE = OGOR V+

\ HOLD N J

TRACK N+1

<CKEOC-*| \~~

«RD— »-| |»- — *4 |-«— <RX
( N DATA )

1CONV-

FIGURE 3. SLOW MEMORY MODE (16-BIT DATA BUS)

1-116

HI-7153/883

Burn-In Circuit

HI-7153/883 CERAMIC DIP

GND •
CLOCK*

NOTES:

R1 , R4, R5 = 1 k£l ±5%, 0.25W (Min)

R2, R3 = 100£J, ±5%, 0.25W (Min)

F1 = F0 + 2, F2 = F1 +2, F3 = F2 + 2 . . . F12 = F11 +2

C1 - C3 = 4.7uF, ±20%

CLOCK = 450kHz (±50kHz) Square Wave With
50% Duty Cycle (+20%), 0V to 2.5V

1-117

HI-7153/883

Metallization Topology

DIE DIMENSIONS:

179x212x19±1mils

METALLIZATION:

Type: Si - Al
Thickness: 11kA±1kA

GLASSIVATION:

Type: Si0 2

Thickness: 8kA± 1kA

DIE ATTACH:

Material: Gold Silicon Eutectic Alloy
Temperature:Ceramic DIP - 460°C (Max)

WORST CASE CURRENT DENSITY:

2.5 x 10 4 A/cm 2

Metallization Mask Layout

HI-7153/883

i i i i # s l ■ * * I n

E-— - . — . - . — . . — — . o o O 00 to

1-118

HI-7153/883

Packaging*

40 PIN CERAMIC DIP

2.035

098 MAX

100
BSC

.515

.535

At*— V*

-Jl .008 ' —I Wis-

.015

. INCREASE MAX UUIT BY .003 INCHES
MEASURED AT CENTER OF FLAT FOR
SOLDER FINISH

LEAD MATERIAL: Type B
LEAD FINISH: Type A

PACKAGE MATERIAL: Ceramic, 90% Alumina
PACKAGE SEAL:

Material: Glass Frit
Temperature: 450°C ± 10°C
Method: Furnace Seal

INTERNAL LEAD WIRE:

Material: Aluminum
Diameter: 1 .25 Mil
Bonding Method: Ultrasonic
COMPLIANT OUTLINE: 38510-D-5

NOTE: All Dimensions are Dimensions are in inches.

t Mil-M-38510 Compliant Materials, Finishes and Dimensions

1-119

Harris Semiconductor

NO. 9203.1 July 1992

Harris Data Acquisition

USING THE HI5800 EVALUATION BOARD

Author: Kantilal Bacrania and Greg Fisher

Theory of Operation

Harris Semiconductor's HI5800 is a new twelve bit sampling
analog to digital converter which is a monolithic alternative to
the many hybrid converters available in the present market.
The converter is a completely self-contained subsystem with
a sample and hold, a curvature corrected band-gap voltage
reference, controller, a 7 bit flash converter, a 14 bit accurate
D/A converter (DAC), wide-band gain amplifier, timing gener-
ator and I/O drivers. It is designed for applications where
high speed and wide bandwidth are essential. It has a con-
version time of -200ns (5MHz) with a throughput rate of
330ns (3MHz). The 12 bit performance is guaranteed over
temperature with no missing codes.

The HI5800 is powered by +5V and -5V supplies with an
input range of -2.5V to +2.5V. Separate chip select and
convert command pins are provided to allow convenient
addressing in multiple converter systems. The 12 bit three
state output is formatted as offset binary with an overflow bit.
The overflow bit indicates over and underflow conditions by
a logic high state. The 12 output bits all remain at logic high
states for overflow and logic low states for underflow
conditions. The digital output bus can be configured to

REFour O

operate either in a parallel 12 bit mode or in an 8 bit mode
where the 8 bit upper byte and 4 bit lower byte are read
sequentially. In either case the HI5800 output data is
available at the end of the conversion cycle with no pipeline
delay or latency. Valid data on the output bus is indicated by
the logic state of the interrupt request output pin. The
converter has fully TTL compatible input buffers for the
digital control pins and also has TTL compatible BiCMOS
output drivers. The output drivers can drive capacitive loads
in excess of 100pF and do not require external data registers
for interfacing to a data bus. The converter allows use of the
internal +2.5V reference or an external reference through
separate reference output and reference input pins. The
voltage appearing on the reference input pin REF, N is
inverted by an internal amplifier to provide the bipolar input
range. The sample and hold offset can be externally
adjusted through the use of 2 offset pins if desired. External
adjustments to the ADC gain at the +2.5V and -2.5V ends of
the input range are also possible through 2 additional pins
provided.

-O do (LSB)
-O D1

-O D2

DIGITAL
OUTPUTS

O D10

-O D11 (MSB)
-O OVF

CONTROL
LOGIC
AND
TIMING

« C

< c

►OIRO

_OCS
-O CONV
-O 51
-O AO

FIGURE 1. HI5800 BLOCK DIAGRAM

1-120

Application Note 9203

The HI5800 is a sampling converter which uses a two step
sub-ranging conversion technique with digital error
correction. A block diagram illustrating the architecture is
shown in Figure 1. The converter uses a high input
impedance (>10M£1) sample and hold at the front end.
During the first pass of the two step conversion process, the
sample and hold output is connected through a switch to a
seven bit bipolar flash analog to digital converter. The flash
converter digitizes the sample and hold output and feeds the
result to the 7 bit digital to analog converter and to a 7 bit
high byte latch. The output of the DAC, which uses thin film
laser trimmed resistors to achieve 14 bit accuracy, is
subtracted from the output of the sample and hold amplifier
and the difference is amplified by a gain of 32. The gain of 32
is realized by two cascaded wide bandwidth op amps. The
output of the second amplifier is now connected through the
switch to the input of the flash converter for the second pass
through the flash. This marks the second step of the two
step conversion process. The flash converter second pass
output is then fed to a seven bit latch which stores the low
byte. The error correction logic takes the two 7 bit words
from the high and low byte latches and computes the final
twelve bit word with overflow detection. The output data is
stored in latches which drive tristate output buffers.

The HI5800 is contro lled with four digital pins: chip select
(CS), convert JCONV), Output Enable (OE) and an output
byte select (AO). Figu re 2 shows the functional timing
diagram for CS, CONV, and OE and the output bits D11-D0,
OVF and output pin IRQ. The CS pin enables the converter
when held low. When CS is held high, the output bits are
tristated and the converter jgnores the states o f the o ther
digital control pins. When CS is held low, the CONV pin
starts the conversion with a negative going edge. In Figure
2, the converter is enabled by dri ving CS low at time to and a
conversion is started by driving CONV low at time t1. The
converter is disabled with all output bits tristate d when CS is
held high as shown at times to and t5. If the CONV pin is
held low after an initial negative going edge, then the

converter will operate in a continuous convert mode with a
self timed sample rate o f just ov er 3MHz. For a synchronous
sampling system, the CONV pin can be driven by an
externally derived system clock at sampling rates of up to
3MHz. Once the conversion is started, the converter's
controller and timing logic control the entire conversion
process until both the present conversion and the next
sample and hold acquisition time are complete. At this time,
approximately 333ns a fter the start of the conversion, the
next falling edge of the CONV pin will be recognized and a
new conversion started. The Interrupt ReQuest (IRQ) pin
allows the user to monitor the conversion process. This
signal goes high upon the start of a conversion for about
200ns indicating that the converter is busy with the conver-
sion. The falling edge of the IRQ pin, at time t2 in Figure 2,
indicates that the new data is present on the output bus. The
converter provides the new data at the end of the current
conversion cycle without any pipeline delays. This feature is
extremely valuable in continuous servo applications when
pipeline latency cannot be tolerated. The output enable pin
OE allows the output drivers to be switched between the
tristate mode and the data valid mode when the chip is
selected. All output pins except for IRQ are tristated with this
function. This function is illustrated at time t3 and t4 in Figure
2. The output bus can be switched between the tristate and
driven modes at any time during the conversion cycle.

A byte select pin (AO) allows eight bit processors to read the
data bus without any need for external logic. The 12 bit
output word can be formatted either in a 12 bit parallel mode
or in an 8 bit mode with the upper and lower bytes read
sequentially. With AO held low, the 12 data bits will appear on
the data pins D11-D0. This is shown in Figure 3 at time t1.
Time t2 in Figure 3 shows that when AO is held high, the
data pins D11-D4 will now output the data bits D3-D0
followed by 4 trailing zeroes. The data bits D3-D0 still remain
on the lower data pins D3-D0. Thus an 8 bit bus can read the
12 bit word through the pins D11-D4 by toggling the AO
control pin.

to 11

CONV

IRQ

011-DO, OVF

t3 14 t5

DATA N-1

\ HIGH Z / \

DATA N y — <T DATA N V

FIGURE 2. HI5800 FUNCTIONAL TIMING DIAGRAM

1-121

Application Note 9203

CONV

IRQ

D11-D4 HIGH Z

FIGURE 3. HI5800 DATA BYTE SELECT DIAGRAM

Description of the Evaluation Board

The evaluation board for the HI5800 is a three layer printed
circuit board specifically designed to facilitate quick
evaluation of the part. The board as supplied has been fitted
with the minimum number of passive components needed to
insure low noise functionality of the converter. The I/O can
be accessed through a 50 pin ribbon cable connector. All
signals except the V !N (analog signal input) and the REF, N
(External Reference input) are brought out on the edge
connector.

Getting Started

In order to minimize lead inductance, make sure the supply
pins and ground are doubly connected on the edge connec-
tor. For the ease of use the HI5800 analog and digital power
supply pins are wired together on the board and do not
require separation for the evaluation board. If desired, the
supplies can be hooked up with external wires to the pins
marked VEE, VCC and GND with up to 16 gauge wire going
to regulated supplies. This is shown in Figure 4.

The four control inputs, CS, AO, CONV, and OE, are all
active low. All four of these inputs are terminated on the
board with 50£2 resistors (R1 , R2, R3, R5) to ground. This
removes the requirement of pulling the lines low with
external signals and also facilitates correct termination with
external signal generators. The analog input V /N is also
terminated with a 50O (R4) resistor near the HI5800 to
ground. Only the V, N terminal is provided with a BNC
connector to interface to the signal source (see Figure 5). If
desired, additional BNC connectors can be added to any of
the control lines, REF| N or IRQ.

Under normal operation, the internal reference can be used
by connecting the shorting jumper plug to the top two pins of
the connector marked X11, see Figure 5. This will connect
the internal 2.5V reference to the converter reference input.
If use of an external reference is desired, then the jumper
plug should be connected to the bottom two pins and the
external reference is fed to the REF| N pin on the board.

FIGURE 4.

The reference and three of the power supply points are
decoupled with 10uF, 0.1 uF and 0.01 uF capacitors in
parallel. The board has further decoupling sockets on every
supply pin which can be utilized to provide better decoupling
in a noisy environment. It is recommended that a good
quality 10uF, 0.1 uF and 0.01 uF in parallel be added to these
points. Figure 6 shows the locations.

The board has jumpers J1 to J4 which ground the offset,
gain and the sample and hold offset pins. These pins can be
used by removing the jumper pins and adding 10kfl potenti-
ometers in the space provided. The board is supplied with
the jumpers installed.

An optional dither output pin is provided to monitor the last
three Isb's of the converter. The resistors need to be
connected in order to exercise this function. The resistor
values for these are: R14 = 1k£l, R12 = 2kfi and R13 = 4kfl.
In using dither, the V, N is swept with the triangular wave and
the oscilloscope X-channel is swept with the same
waveform. The Y-channel is connected to the dither out pin.
The resultant waveform is shown in Figure 8.

1-122

Application Note 9203

FIGURE 6.

1-123

Application Note 9203

The edge connector carries all the digital input and output
signals (see Figure 7). The pins marked NC do not carry any
signals. If desired, these pins can be used to feed any of the
other pins that are not brought out to the connector. Each of
the pins on the left side of the connector is grounded which
allows convenient termination if desired.

DITHE
OUT

CONNECTOR

FIGURE 7.

NOTE: The device is static sensitive and adequate precautions
should be taken when handling the part.

Using the Evaluation Board

The board can be used in a stand alone mode. Make sure
the ±5V power supplies and ground are present. The input to
the converter is +2.5V maximum and is connected to the V| N
connector. The conversion is started by applying a negative
going p ulse to the convert line. For continuous convert, the
CONV line can be held low after the first transition to zero. At
the beginning of a conversion, the IRQ line will go high for
approximately 200ns and return to zero. At each of the falling
edges of the IRQ signal, new data is available on the bus.
The data can be accessed through the edge connector. One
of the easy ways to reconstruct the data is by reading the
digital outputs with a logic analyzer with charting capability
(like the Hewlett Packard 1652) and observing the output
states. The IRQ output is used as clock qualifier. This allows
the input waveform to be reconstructed and displayed. Also,
a high speed 12-bit digital to analog converter (HI-562A) can
be connected to the output bus and the DAC output
observed on a scope.

The conve rter can also be used in a triggered mode where
the CONV pulse is a negative going pulse with a pulse
width of 25ns to 300ns and period of >330ns. Again, at
each start of conversion, the IRQ will go high for ~200ns.
The CONV pulse should go high before the end of the
acquisition period which is -100ns aft er the IRQ goes low.
In order to start a new conversion, the CONV line should go
negative again. The data can be accessed at any time on
the data bus.

The only adjustments on the board are the three potentiome-
ters which can control the offset, gain and the Sample and
Hold offset of the converter. The offset and sample/hold off-
set trims adjust the voltage offset of the transfer curve while
the gain trim adjusts the tilt of the transfer curve around the
curve midpoint (code 2048). The 10kQ potentiometers can
be installed to achieve the desired adjustment in the follow-
ing manner. The offset trimpot should be adjusted to get
code 2048 centered at a desired DC input voltage such as
zero volts. Next the gain trim can be adjusted by trimming
the gain pot until the 4094 to 4095 code transition occurs at
the desired voltage (2.500 - 1.5LSBs for a 2.5V reference).
The gain trim can also be done by adjusting the gain pot until
the code to 1 transition occurs at a particular voltage (-2.5
+0.5LSBs for a 2.5V reference). If a nonzero offset is
needed, then the offset pot or the sample/hold offset pot can
be adjusted after the gain trim is finished. The gain trim is
simplified if an offset trim to zero is done first and then a non-
zero offset trim is done. The offset and sample/hold offset
trimpots have an identical effect on the converter except that
the sample/hold offset is a finer resolution trim.

Pin Description and
Typical Evaluation Data

The pin description is presented in Table 1. This is followed
by some evaluation curves on typical performance of
HI5800.

1-124

Application Note 9203

TABLE 1. PIN DESCRIPTION

44 PIN
PLCC

40 PIN
CERDIP

PIN
NAME

PIN DESCRIPTION

REF IN

External reference input.

R°adj

DAC offset adjust.

RGadj

DAC gain adjust.

AV CC

Analog positive power supply, +5V

REF 0UT

Internal reference output, +2.5V.

No connection.

Vin

Analog input voltage.

AGND

Analog ground.

ADJ+

Sample/hold offset adjust.

ADJ-

Sample/hold offset adjust.

AV EE

Analog negative power supply, -5V

AV CC

Analog positive power supply, +5V

AGND

Analog ground.

AV EE

Analog negative power supply, -5V

Output byte control input, active low. When low, data is presented as a 12 bit word or the upper byte
(D11-D4) in 8 bit mode. When high, the second byte contains the lower LSB's (D3-D0) with 4 trailing
zeroes. See Text.

Chip Select input, active low. Dominates all control inputs.

No connection.

Output Enable input, active low.

CONV

Convert start input. Initiates conversion on the falling edge. If held low, continuous conversion mode
overrides and remains in effect until the input goes high.

DV EE

Digital negative power supply, -5V.

DGND

Digital ground.

DV CC

Digital positive power supply, +5V.

AV CC

Analog positive power supply, +5V.

Data bit 0, (LSB).

Data bit 1.

Data bit 2.

Data bit 3.

No connection

Data bit 4.

Data bit 5.

Data bit 6.

Data bit 7.

AV EE

Analog negative power supply, -5V.

AGND

Analog ground.

DGND

Digital ground.

DV CC

Digital positive power supply, +5V.

Data bit 8.

Data bit 9.

No connection.

m n

U I u

Hata Kit 1 n

uaid on i u.

D11

Data bit 11 (MSB).

av cc

Analog positive power supply, +5V.

OVF

Overflow output. Active high when either an overrange or underrange analog input conditions is detected.

IRQ

Interrupt ReQuest output. Goes low when a conversion is complete.

1-125

Application Note 9203

Typical Performance Curves

TYPICAL SNH vs INPUT FREQUENCY

TYPICAL THD v« INPUT FREQUENCY

30
20
10

INPUT FREQUENCY (Hz)

500K 1M
INPUT FREQUENCY (Hz)

TYPICAL SND vs INPUT FREQUENCY

TYPICAL SPDF vs INPUT FREQUENCY

80
70
60
50
40
30
20
10

20K

500K 1M
INPUT FREQUENCY (Hz)

TYPICAL EFFECTIVE BITS vs INPUT FREQUENCY

S 6
£ 4

>00K 1M
INPUT FREQENCY (Hz)

1-126

Application Note 9203

Typical Performance Curves (continued)

DIFFERENTIAL NON-LINEARITY INTEGRAL NON-LINEARITY

FFT SPECTRAL PLOT FOR F w = 2MHz, F s = 3MH

10 . , ,

o I I i

3S5K 730K 1.095M 1.4SM

FREQUENCY (Hz)

1-127

Application Note 9203

Silk Screen

OFFSET GAIN SH VIO

0<SND

VlN

REF,N

□ □

□ O AO

□ □ 55

VEE O VEE
VEE

vcc

vcc Ovcc

NC
NC

□ □

□ n

□ □

CONV

D€

D10

D11

OVF

IRQ

O-CD-O

O-CD- O

O-CD-O

R14

h° o 3

DITHER o T U
OUT pfti

C29I

C2SI

1C24

)C27

SEMICONDUCTOR

Application Note 9203

P4 (?) DITHER OUT

C23 > |+IOuF

C22. ,

CI |.Q1|iF

EXT REF

v«0-

I — X1 — * t

,,_ ran I M ," v

V vcc ■

R9
10K

R10
10K

R11

Hisaoo

(22) (LSB)DO

(23) Dt

REFJN (1) ,,4,0,
REF_0UT(5) (25) D3

(26) D4

AGND (7)
(12)

(27) D5

(28) D6

(J1)
DGND (19)

(29)07

(34) D9

DGND (32)

(35) D9

V,N (6)

(36) D10

(37)(MS8)D11

(40) IRQ
(tt)OVF

CONV (17)

OE (16)
SO (14)
£5 (15)

RO_ADJ(2)

(

RG_ADJ(3)

(1S)DVEE

(33)DVCC

(20)DVCC

(4) AVCC
(11) AVCC

(21) AVCC

(3«) AVCC

ADJ. (8)
ADJ-(»)

(10) AVEE
(13)AVEE
(30)

R12
IK

R13
2K

-ED— |
-0 —
-0— >
-0— '
-ED—
-0— ■

4x71-

D11

"0— '
"0

-HID— :

si* 8 *

it "

JJ o » .

5 I P 0-

7 rn Z

IB 5. o38

sills

li I 3
11

a o o>
z o!
o z o
z J
m o

mi —

0- 1

OVF

VEE

iTTWW

r I csi |cr |,gq^r;

*1 1 C10 1? ■oiTT'^'Tca v

C29
10fiF

10tiF

CS1| |C2 J,C2S

cisj_ c

mfL^J,,

C17|_

C1S| Ici6| + jiTMai

=!==!= 4= "^r-W

if T-iyrTca
9_J_ JC20jf ^^T - '«MF

*11-Ji I

ciirrt^riM^H

iT TiufXWi v

C32
10(iF

C26 V
10nF

Application Note 9203

Materials List

Program: PC-FORM VERSION 5.10

Date : Apr 21 1992

Time :01:07:27 PM

File In : 5800D.PNL

File Out : 5800D. MAT

Format : P-CAD MATERIALS LIST

ITEM

QTY

PART NAME

REFERENCE DESIGNATOR

DESCRIPTION

CK06

C1, C3, C5, C6, C8, 011, C14, C15, C17, C19, C21

VAL=.01nF

CK06

C4, C7, C9, C10, C12, C13, C16, C18, C20, C2, C22

VAL = .1tiF

RC05

R2, R3, R5, R1.R4

VAL = 50fl

RC05

R12

VAL = 2K

RC05

R13

VAL = 4K

RC05

R14

VAL= 1K

50RCONGT

50 PIN RIBBON CONNECTOR

PCAP

C24. C25, C23, C26, C27, C28, C29, C30, C31, C32, C33

VAL= 10(iF

TRMPOT

R11, R9, R10

VAL= 10K

RBNC

P1, P2, P3, P4, P6, P7, P8, P9, P10

3PINJUMP

X11

HI5800

1-131

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